| Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008) |
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| 04/29/2003 | US6556066 Boosting method and apparatus |
| 04/29/2003 | US6556065 256 Meg dynamic random access memory |
| 04/29/2003 | US6556051 Apparatus for providing both supports including synchronous dynamic random access memory (SDRAM) module and double data rate (DDR) DRAM module |
| 04/29/2003 | US6555882 Semiconductor element and semiconductor memory device using the same |
| 04/24/2003 | WO2003034496A1 Information recorder and electronic apparatus with mounted information recorder |
| 04/24/2003 | WO2003034437A2 Writing to a mram element comprising a synthetic antiferromagnetic layer |
| 04/24/2003 | WO2003034436A2 Semiconductor storage unit provided with intersecting word and bit lines whereon are arranged magnetoresistive memory cells |
| 04/24/2003 | WO2003034435A1 Low power auto-refresh circuit and method for dynamic random access memories |
| 04/24/2003 | WO2003033687A2 Lift-off process for a hard etch mask for magnetic memory cells in mram devices |
| 04/24/2003 | WO2002101747A3 Draw with bit line precharging, inverting data writing, retained data output and reduced power consumption |
| 04/24/2003 | WO2002043072A3 Very small swing and low voltage cmos static memory |
| 04/24/2003 | US20030079155 System and method for efficient lock recovery |
| 04/24/2003 | US20030079111 Device for linking a processor to a memory element and memory element |
| 04/24/2003 | US20030079095 Triggering of IO equilibrating ending signal with firing of column access signal |
| 04/24/2003 | US20030077537 Integrated circuits; random access memory |
| 04/24/2003 | US20030076731 Multiport semiconductor memory |
| 04/24/2003 | US20030076729 Method and apparatus for reducing average power and increasing cache performance by modulating power supplies |
| 04/24/2003 | US20030076728 Semiconductor device having test mode |
| 04/24/2003 | US20030076727 Apparatus and method for refresh and data input device in SRAM having storage capacitor cell |
| 04/24/2003 | US20030076726 Low power auto-refresh circuit and method for dynamic random access memories |
| 04/24/2003 | US20030076725 System and method for power saving memory refresh for dynamic random access memory devices after an extended interval |
| 04/24/2003 | US20030076724 Semiconductor memory device and test method therof |
| 04/24/2003 | US20030076721 Sense amplifier with improved read access |
| 04/24/2003 | US20030076720 First bit databurst firing of IO equilibrating ending signal based on column access signal |
| 04/24/2003 | US20030076718 Method for storing and reading data in a multilevel nonvolatile memory, and architecture therefor |
| 04/24/2003 | US20030076715 Semiconductor memory device |
| 04/24/2003 | US20030076714 Semiconductor integrated circuit, and a data storing method thereof |
| 04/24/2003 | US20030076712 Memory device and process for improving the state of a termination |
| 04/24/2003 | US20030076711 Semiconductor memory device |
| 04/24/2003 | US20030076709 Method for operating a multi-level memory cell |
| 04/24/2003 | US20030076708 Thin film magnetic memory device including memory cells having a magnetic tunnel junction |
| 04/24/2003 | US20030076707 Single transistor type magnetic random access memory device and method of operating and manufacturing the same |
| 04/24/2003 | US20030076706 Semiconductor device |
| 04/24/2003 | US20030076705 Semiconductor device |
| 04/24/2003 | US20030076704 Ferroelectric memory and method of operating same |
| 04/24/2003 | US20030076703 Magnetic random access memory |
| 04/24/2003 | US20030076702 Semiconductor memory device having first and second memory architecture and memory system using the same |
| 04/24/2003 | US20030076701 Method and apparatus for reducing average power in RAMs by dynamically changing the bias on PFETs contained in memory cells |
| 04/24/2003 | US20030076156 Method and circuit for generating a high voltage |
| 04/24/2003 | US20030076142 Delay locked loop with multi-phases |
| 04/24/2003 | US20030076117 Method and circuit for reading data from a ferroelectric memory cell |
| 04/24/2003 | US20030075797 Semiconductor device and method of manufacturing the same |
| 04/24/2003 | US20030075789 Semiconductor storage device having memory chips in a stacked structure |
| 04/24/2003 | US20030075778 Programmable resistance memory element and method for making same |
| 04/24/2003 | US20030075773 Semiconductor memory device |
| 04/24/2003 | US20030075738 Twin bit cell flash memory device and its fabricating method |
| 04/23/2003 | EP1304738A2 Single transistor type magnetic random access memory device and method of operating and manufacturing the same |
| 04/23/2003 | EP1304701A1 Sensing circuit for ferroelectric non-volatile memories |
| 04/23/2003 | EP1303877A2 Semiconductor memory architecture |
| 04/23/2003 | EP1125300B1 Method and apparatus for increasing the time available for refresh for 1-t sram compatible devices |
| 04/23/2003 | EP1103051B1 Ferroelectric storage assembly |
| 04/23/2003 | EP1099222B1 Ferroelectric read/write memory having series-connected storage cells (cfram) |
| 04/23/2003 | EP0740854B1 A self-aligned dual-bit split gate (dsg) flash eeprom cell |
| 04/23/2003 | CN1412863A Method for modifying magnetic tunnel junction conversion characteristics |
| 04/23/2003 | CN1412849A Semiconductor |
| 04/23/2003 | CN1412847A Single transistor type magnetic random access memory and its operating and mfg. method |
| 04/23/2003 | CN1412777A High density memory read amplifier |
| 04/23/2003 | CN1412151A Ferroelectric storage material perovskite type SrBi2 Ta2O9 aramic powder and its preparation method |
| 04/23/2003 | CN1106648C Semiconductor integrated circuit having test circuit |
| 04/23/2003 | CN1106647C Voltage multiplier |
| 04/23/2003 | CN1106635C 磁电阻效应元件 Magnetoresistance effect element |
| 04/22/2003 | US6553520 Integrated circuit devices with mode-selective external signal routing capabilities and methods of operation therefor |
| 04/22/2003 | US6553467 Bank information pre-decode apparatus |
| 04/22/2003 | US6553449 System and method for providing concurrent row and column commands |
| 04/22/2003 | US6552959 Semiconductor memory device operable for both of CAS latencies of one and more than one |
| 04/22/2003 | US6552958 Semiconductor integrated circuit device |
| 04/22/2003 | US6552957 Semiconductor integrated circuit having a signal receiving circuit |
| 04/22/2003 | US6552954 Semiconductor integrated circuit device |
| 04/22/2003 | US6552949 Reducing leakage current in a memory device |
| 04/22/2003 | US6552945 Method for storing a temperature threshold in an integrated circuit, method for storing a temperature threshold in a dynamic random access memory, method of modifying dynamic random access memory operation in response to temperature, programmable temperature sensing circuit and memory integrated circuit |
| 04/22/2003 | US6552944 Single bitline direct sensing architecture for high speed memory device |
| 04/22/2003 | US6552943 Sense amplifier for dynamic random access memory (“DRAM”) devices having enhanced read and write speed |
| 04/22/2003 | US6552932 Segmented metal bitlines |
| 04/22/2003 | US6552930 Semiconductor memory device and storage method thereof |
| 04/22/2003 | US6552929 Piggyback programming using an extended first pulse for multi-level cell flash memory designs |
| 04/22/2003 | US6552928 Read-write control circuit for magnetic tunnel junction MRAM |
| 04/22/2003 | US6552927 MRAM architecture and system |
| 04/22/2003 | US6552926 Magnetic random-access memory |
| 04/22/2003 | US6552925 Method of reading a four-transistor memory cell array |
| 04/22/2003 | US6552924 Method of reading and logically OR'ing or AND'ing a four-transistor memory cell array by rows or columns |
| 04/22/2003 | US6552923 SRAM with write-back on read |
| 04/22/2003 | US6552922 Chain-type ferroelectric random access memory (FRAM) with rewrite transistors coupled between a sense amplifier and a bit line pair |
| 04/22/2003 | US6552921 Circuit to simulate the polarization relaxation phenomenon of the ferroelectric memory |
| 04/22/2003 | US6552887 Voltage dependent capacitor configuration for higher soft error rate tolerance |
| 04/22/2003 | US6552587 Synchronous semiconductor device for adjusting phase offset in a delay locked loop |
| 04/22/2003 | US6552401 Use of gate electrode workfunction to improve DRAM refresh |
| 04/22/2003 | US6552357 Semiconductor memory device having plate lines and precharge circuits |
| 04/22/2003 | US6551852 Method of forming a recessed magnetic storage element |
| 04/22/2003 | US6551846 Semiconductor memory device capable of correctly and surely effecting voltage stress acceleration |
| 04/22/2003 | CA2294164C Optical logic element and methods for respectively its preparation and optical addressing, as well as the use thereof in an optical logic device |
| 04/17/2003 | WO2003032392A2 Programmable microelectronic device, structure, and system, and method of forming the same |
| 04/17/2003 | WO2003032338A1 Spin-valve magnetoresistive device with enhanced performance |
| 04/17/2003 | WO2003032336A1 Magnetic elements with magnetic flux closure, production method and memory application |
| 04/17/2003 | WO2003032323A1 Ferrodielectric non-volatile semiconductor memory |
| 04/17/2003 | WO2003032322A2 Adjustable memory self-timing circuit |
| 04/17/2003 | WO2003032170A1 Asynchronous hidden refresh of semiconductor memory |
| 04/17/2003 | WO2003032054A1 Magnetooptic element employing spin chirality |
| 04/17/2003 | WO2003005369A3 Molecular electronics arrangement and method for producing a molecular electronics arrangement |
| 04/17/2003 | WO2002080183A3 Memory cell structural test |
| 04/17/2003 | WO2002033706A3 Noise suppression for open bit line dram architectures |