Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
04/2003
04/03/2003US20030062948 Semiconductor integrated circuit
04/03/2003US20030062944 High-speed bank select multiplexer latch
04/03/2003US20030062942 Input circuit and semiconductor integrated circuit having the input circuit
04/03/2003US20030062905 Circuit configuration and method for assessing capacitances in matrices
04/03/2003US20030062576 Semiconductor integrated circuit device
04/03/2003US20030062559 Semiconductor device
04/03/2003US20030062556 Memory array employing integral isolation transistors
04/03/2003US20030062553 Epitaxial template and barrier for the integration of functional thin film metal oxide heterostructures on silicon
04/03/2003US20030062552 Reset apparatus, semiconductor ic apparatus, and semiconductor memory apparatus
04/03/2003CA2461015A1 A system and method for a multi-node environment with shared storage
04/02/2003EP1298671A2 Bit line control decoder circuit, virtual ground type nonvolatile semiconductor storage device provided with the decoder circuit, and data read method of virtual ground type nonvolatile semiconductor storage device
04/02/2003EP1298670A1 Method for storing and reading data in a multilevel nonvolatile memory with a non-binary number of levels, and architecture therefor
04/02/2003EP1298669A2 Magnetic memory device
04/02/2003EP1298668A2 Semiconductor memory device including clock-independent sense amplifier
04/02/2003EP1298667A2 Semiconductor memory device
04/02/2003EP1297533A1 Magnetic memory
04/02/2003EP1297532A2 Dynamic random access memory
04/02/2003EP1141736B1 Pattern generator for a packet-based memory tester
04/02/2003CN1408118A Improved high density memory cell
04/02/2003CN1407614A Operation of programmed and erasing P-channel SONOS memory unit
04/02/2003CN1407560A Semiconductor device equiped with memory and logical chips for testing memory ships
04/02/2003CN1407558A 半导体存储器 Semiconductor memory
04/02/2003CN1407557A Method and structure for maximizing SN ratio of electric resistance array
04/02/2003CN1104778C Convolutional interieaver and method for generating address
04/02/2003CN1104727C Storage device with layered position-line
04/01/2003US6542969 Memory controller and a cache for accessing a main memory, and a system and a method for controlling the main memory
04/01/2003US6542959 Memory refreshing system
04/01/2003US6542957 Memory of controlling page mode access
04/01/2003US6542645 Adaptive tracking of dots in optical storage system using ink dots
04/01/2003US6542433 Column address buffering circuit
04/01/2003US6542432 Sub word line drive circuit for semiconductor memory device
04/01/2003US6542428 Semiconductor memory device allowing increase in capacity and operation speed with a suppressed layout area
04/01/2003US6542426 Cell data protection circuit in semiconductor memory device and method of driving refresh mode
04/01/2003US6542425 Refresh control circuit for controlling refresh cycles according to values stored in a register and related refreshing method
04/01/2003US6542424 Semiconductor integrated circuit device using static memory cells with bit line pre-amplifier and main amplifier
04/01/2003US6542422 Semiconductor memory device performing high speed coincidence comparison operation with defective memory cell address
04/01/2003US6542417 Semiconductor memory and method for controlling the same
04/01/2003US6542416 Methods and arrangements for conditionally enforcing CAS latencies in memory devices
04/01/2003US6542415 Kickb signal generator
04/01/2003US6542412 Process for making and programming and operating a dual-bit multi-level ballistic flash memory
04/01/2003US6542407 Techniques of recovering data from memory cells affected by field coupling with adjacent memory cells
04/01/2003US6542405 Semiconductor memory device having faulty cells
04/01/2003US6542404 Small size, low consumption, multilevel nonvolatile memory
04/01/2003US6542403 Piggyback programming using voltage control for multi-level cell flash memory designs
04/01/2003US6542402 Thin film magnetic memory device capable of easily controlling a data write current
04/01/2003US6542401 SRAM device
04/01/2003US6542399 Apparatus and method for pumping memory cells in a memory
04/01/2003US6542398 Magnetic random access memory
04/01/2003US6542011 Driver circuit, receiver circuit, and semiconductor integrated circuit device
04/01/2003US6541811 Capacitor/antifuse structure having a barrier-layer electrode and improved barrier layer
03/2003
03/27/2003WO2003025949A1 Selective operation of a multi-state non-volatile memory system in a binary mode
03/27/2003WO2003025948A1 Variable level memory
03/27/2003WO2003025947A2 Edram based architecture
03/27/2003WO2003025946A1 Magnetic memory with write inhibit selection and the writing method for same
03/27/2003WO2003025945A2 Compensation of a bias magnetic field in a storage surface of a magnetoresistive storage cell
03/27/2003WO2003025944A1 Semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric
03/27/2003WO2003025943A1 Magnetic memory device and its recording control method
03/27/2003WO2003025942A2 Magnetic memory with spin-polarized current writing, using amorphous ferromagnetic alloys, writing method for same
03/27/2003WO2003025938A1 Low-power, high-density semiconductor memory device
03/27/2003WO2003025937A2 Background operation for memory cells
03/27/2003WO2003025801A1 System and method for implementing journaling in a multi-node environment
03/27/2003WO2003025780A1 System and method for journal recovery for multinode environments
03/27/2003WO2003025751A1 A system and method for efficient lock recovery
03/27/2003WO2003025600A1 Multilevel signal interface testing with binary test apparatus by emulation of multilevel signals
03/27/2003WO2003025599A1 Built-in self-testing of multilevel signal interfaces
03/27/2003US20030061560 Method for error detection/correction of multilevel cell memory and multilevel cell memory having error detection/correction function
03/27/2003US20030061536 Power controlling method for semiconductor storage device and semiconductor storage device employing same
03/27/2003US20030061528 Method and system for controlling clock signals in a memory controller
03/27/2003US20030060934 Method and apparatus for regulation of electrical component temperature through component communication throttling based on corrected sensor information
03/27/2003US20030059588 Electron spin mechanisms for inducing magnetic-polarization reversal
03/27/2003US20030058732 Semiconductor memory device with an adaptive output driver
03/27/2003US20030058731 Semiconductor memory device having clock generator for controlling memory and method of generating clock signal
03/27/2003US20030058730 Semiconductor memory device and its testing method
03/27/2003US20030058729 Semiconductor integrated circuit device
03/27/2003US20030058728 Wide dynamic range and high speed voltage mode sensing for a multilevel digital non-volatile memory
03/27/2003US20030058727 Semiconductor memory device capable of rewriting data signal
03/27/2003US20030058726 Semiconductor storage unit
03/27/2003US20030058724 Reduced current address selection circuit and method
03/27/2003US20030058722 Semiconductor memory device and method for driving a sense amplifier
03/27/2003US20030058720 Semiconductor memory device with stable precharge voltage level of data lines
03/27/2003US20030058719 Semiconductor memory device including clock-independent sense amplifier
03/27/2003US20030058717 Word-line deficiency detection method for semiconductor memory device
03/27/2003US20030058712 Bit line control decoder circuit, virtual ground type nonvolatile semiconductor storage device provided with the decoder circuit, and data read method of virtual ground type nonvolatile semiconductor storage device
03/27/2003US20030058710 Semiconductor memory device
03/27/2003US20030058702 Method of reading and restoring data stored in a ferroelectric memory cell
03/27/2003US20030058701 Semiconductor memory device and various systems mounting them
03/27/2003US20030058698 Memory with high performance unit architecture
03/27/2003US20030058697 Programmable molecular device
03/27/2003US20030058696 Semiconductor memory device having reduced chip select output time
03/27/2003US20030058695 Semiconductor memory device capable of masking undesired column access signal
03/27/2003US20030058686 Thin film magnetic memory device sharing an access element by a plurality of memory cells
03/27/2003US20030058685 Read methods for magneto-resistive device having soft reference layer
03/27/2003US20030058684 Magneto-resistive device having soft reference layer
03/27/2003US20030058683 Ferroelectric-type nonvolatile semiconductor memory
03/27/2003US20030058682 Circuit to simulate the polarization relaxation phenomenon of the ferroelectric memory
03/27/2003US20030058681 Mechanism for efficient wearout counters in destructive readout memory
03/27/2003US20030058676 Semiconductor integrated circuit device and semiconductor device system
03/27/2003US20030058675 Silicon-on-insulator SRAM cells with increased stability and yield
03/27/2003US20030058563 SDRAM interface control system and method
03/27/2003US20030058032 Semiconductor integrated circuit and semiconductor memory having a voltage step-down circuit stepping external power supply voltage down to internal power supply voltage
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