Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
03/2003
03/27/2003US20030058029 Voltage boosting circuit with two main charge pumps
03/27/2003US20030058020 Semiconductor device capable of reducing noise to signal line
03/27/2003US20030058016 Operation control according to temperature variation in integrated circuit
03/27/2003US20030057500 Semiconductor memory device
03/27/2003US20030057461 Magneto-resistive device including soft synthetic ferrimagnet reference layer
03/27/2003US20030057423 Three-dimensional device
03/27/2003US20030056668 Digital print media output with reduced residual curl
03/27/2003DE19830571C2 Integrierte Schaltung Integrated circuit
03/27/2003CA2461018A1 Edram based architecture
03/27/2003CA2460833A1 System and method for implementing journaling in a multi-node environment
03/26/2003EP1296332A2 Magnetic memory device
03/26/2003EP1296331A2 Method of performing MRAM read operation
03/26/2003EP1295394A2 Block ram having multiple configurable write modes for use in a field programmable gate array
03/26/2003EP1021794A4 A camera with internal printing system
03/26/2003CN1406003A Semiconductor integrated apparatus and delayed locking ring device
03/26/2003CN1405889A 同步型半导体存储装置 Synchronous type semiconductor memory device
03/26/2003CN1405777A Multiple-location storage unit
03/26/2003CN1405776A Semiconductor integrated circuit and storage system thereof
03/26/2003CN1405650A Interpolating circuit and DLL circuit and semi-conductor integrated cirucit
03/26/2003CN1104053C Semiconductor IC
03/26/2003CN1104052C Semiconductor device
03/26/2003CN1104010C Method for programming nonvolatile memory unit
03/26/2003CN1103950C Voltage generation circuit that can stably generate intermediate potential independent of theshold voltage
03/25/2003US6539452 Semiconductor redundant memory provided in common
03/25/2003US6538956 Semiconductor memory device for providing address access time and data access time at a high speed
03/25/2003US6538955 Semiconductor integrated circuit for which high voltage countermeasure was taken
03/25/2003US6538954 Multi-port static random access memory equipped with a write control line
03/25/2003US6538953 Semiconductor memory device
03/25/2003US6538952 Random access memory with divided memory banks and data read/write architecture therefor
03/25/2003US6538951 Dram active termination control
03/25/2003US6538950 Integrated memory and corresponding operating method
03/25/2003US6538949 Device and method for repairing a memory array by storing each bit in multiple memory cells in the array
03/25/2003US6538948 Semiconductor device, refreshing method thereof, memory system, and electronic instrument
03/25/2003US6538946 Semiconductor integrated circuit device
03/25/2003US6538945 Sense amplifiers having reduced Vth deviation
03/25/2003US6538944 Semiconductor memory device having a word line enable sensing circuit
03/25/2003US6538942 Process for controlling a read access for a dynamic random access memory and corresponding memory
03/25/2003US6538941 Semiconductor memory device and method of pre-charging I/O lines
03/25/2003US6538940 Method and circuitry for identifying weak bits in an MRAM
03/25/2003US6538936 Semiconductor integrated circuit having test circuit
03/25/2003US6538933 High speed semiconductor memory device with short word line switching time
03/25/2003US6538932 Timing circuit and method for a compilable DRAM
03/25/2003US6538928 Method for reducing the width of a global data bus in a memory architecture
03/25/2003US6538924 Semiconductor integrated circuit
03/25/2003US6538923 Staircase program verify for multi-level cell flash memory designs
03/25/2003US6538922 Writable tracking cells
03/25/2003US6538921 Circuit selection of magnetic memory cells and related cell structures
03/25/2003US6538920 Cladded read conductor for a pinned-on-the-fly soft reference layer
03/25/2003US6538918 Pulsed write techniques for magneto-resistive memories
03/25/2003US6538917 Read methods for magneto-resistive device having soft reference layer
03/25/2003US6538916 Semiconductor memory device
03/25/2003US6538915 Semiconductor integrated circuit device
03/25/2003US6538914 Ferroelectric memory with bit-plate parallel architecture and operating method thereof
03/25/2003US6538913 Method for operating a ferroelectric memory configuration and a ferroelectric memory configuration
03/25/2003US6538912 Semiconductor device
03/25/2003US6538494 Pump circuits using flyback effect from integrated inductance
03/25/2003US6538493 Semiconductor integrated circuit
03/25/2003US6538482 Voltage detection circuit, power-on/off reset circuit, and semiconductor device
03/25/2003US6538476 Method of forming a pseudo-differential current sense amplifier with hysteresis
03/25/2003US6538297 Magneto-resistive device and magneto-resistive effect type storage device
03/25/2003US6537877 Semiconductor memory device
03/20/2003WO2002089140A3 Method and apparatus for completely hiding refresh operations in a dram device using multiple clock division
03/20/2003WO2002015195A3 Method and apparatus for controlling a read valid window of a synchronous memory device
03/20/2003US20030056078 Ferroelectric memory circuit and method for its fabrication
03/20/2003US20030056067 System and method for managing data in memory for reducing power consumption
03/20/2003US20030056053 Low power semiconductor memory device having a normal mode and a partial array self refresh mode
03/20/2003US20030056042 Semiconductor memory unit
03/20/2003US20030056040 Two step memory device command buffer apparatus and method and memory devices and computer systems using same
03/20/2003US20030053400 Dielectric information apparatus, tape-like medium recording/reproducing apparatus and disc-like medium recording/reproducing apparatus
03/20/2003US20030053366 Circuit for generating internal address in semiconductor memory device
03/20/2003US20030053365 Apparatus and method for inputting address signals in semiconductor memory device
03/20/2003US20030053363 Semiconductor integrated circuit
03/20/2003US20030053362 Synchronous semiconductor memory device
03/20/2003US20030053361 EDRAM based architecture
03/20/2003US20030053360 Semiconductor memory device
03/20/2003US20030053357 Nonvolatile semiconductor memory device having ferroelectric capacitors
03/20/2003US20030053356 Non-volatile memory and method of non-volatile memory programming
03/20/2003US20030053351 Ferroelectric memory device and method for manufacturing the same
03/20/2003US20030053350 Memory device
03/20/2003US20030053342 Command decoder and decoding method for use in semiconductor memory device
03/20/2003US20030053341 Distributed cell plate and/or digit equilibrate voltage generator
03/20/2003US20030053340 DDR sdram for stable read operation
03/20/2003US20030053334 Selective operation of a multi-state non-volatile memory system in a a binary mode
03/20/2003US20030053333 Variable level memory
03/20/2003US20030053331 Magnetoresistive level generator and method
03/20/2003US20030053330 Dual capacitor dynamic random access memory cell
03/20/2003US20030053329 Low-power, high-density semiconductor memory device
03/20/2003US20030053328 Column repair circuit in ferroelectric memory
03/20/2003US20030053327 Nonvolatile ferroelectric memory and method for driving the same
03/20/2003US20030053326 Ferroelectric storage device
03/20/2003US20030053325 Content-addressable memory device
03/20/2003US20030052735 Ferroelectric memory device and a method for driving the same
03/20/2003US20030052719 Digital delay line and delay locked loop using the digital delay line
03/20/2003US20030052718 Interpolating circuit, DLL circuit and semiconductor integrated circuit
03/20/2003US20030052660 Internal step-down power supply circuit
03/20/2003US20030052656 Regulator circuit for independent adjustment of pumps in multiple modes of operation
03/20/2003US20030052369 Semiconductor output circuit device
03/20/2003US20030052361 Triple self-aligned split-gate non-volatile memory device
03/20/2003US20030052354 Use of gate electrode workfunction to improve DRAM refresh
03/20/2003US20030052344 Evaluation configuration for semiconductor memories
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