| Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008) |
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| 04/08/2004 | US20040066682 Reading ferroelectric memory cells |
| 04/08/2004 | US20040066680 Non-volatile semiconductor memory device adapted to store a multi-valued data in a single memory cell |
| 04/08/2004 | US20040066678 Magnetic memory device implementing read operation tolerant to bitline clamp voltage (VREF) |
| 04/08/2004 | US20040066676 SRAM-compatible memory for correcting invalid output data using parity and method of driving the same |
| 04/08/2004 | US20040066669 Semiconductor device saving data in non-volatile manner during standby |
| 04/08/2004 | US20040066668 Antiferromagnetically coupled bi-layer sensor for magnetic random access memory |
| 04/08/2004 | US20040066667 Write current shunting compensation |
| 04/08/2004 | US20040066666 Structure and method of vertical transistor DRAM cell having a low leakage buried strap |
| 04/08/2004 | US20040066213 Integrated circuit devices having data inversion circuits therein that reduce simultaneous switching noise and support interleaving of parallel data |
| 04/08/2004 | US20040065914 Semiconductor device and method of fabricating the same |
| 04/08/2004 | US20040065913 Memory device |
| 04/08/2004 | US20040065912 Electrically programmable nonvolatile variable capacitor |
| 04/08/2004 | US20040065906 Semiconductor integrated circuit device |
| 04/08/2004 | US20040065904 Data inversion circuit and semiconductor device |
| 04/08/2004 | US20040065818 High-density data storage medium, method of manufacturing the data storage medium, data storage apparatus, and methods of writing data on, and reading and erasing data from the data storage medium by using the data storage apparatus |
| 04/08/2004 | US20040065738 Data distribution mechanism in the form of ink dots on cards |
| 04/08/2004 | DE19825034B4 Pegelumsetzerschaltung Level shift circuit |
| 04/08/2004 | DE19748023B4 Zeilendecodierer für Halbleiterspeichereinrichtung Row decoder for the semiconductor memory device |
| 04/08/2004 | DE10345116A1 Bitleitungsausgleichssystem für eine integrierte DRAM-Schaltung Bitleitungsausgleichssystem for a DRAM integrated circuit |
| 04/08/2004 | DE10330111A1 Verfahren eines selbstreparierenden dynamischen Direktzugriffsspeichers A method of self-repairing dynamic random access memory |
| 04/08/2004 | DE10245538A1 DRAM cell configuration has connecting line that electrically connects active regions of two selection transistors of adjacent rows, to form common terminal region for two trench capacitors |
| 04/08/2004 | DE10245248A1 Semiconductor memory module for acting as a dual in-line memory module has multiple dynamic or static/shadow RAM components and memory parameter devices |
| 04/08/2004 | DE10245037A1 Design and manufacture procedure for semiconductor memory building blocks involves designing first and second layouts and using one layout for entire design layout |
| 04/08/2004 | DE10158271B4 Halbleiterschaltungsanordnung mit Abschlussimpedanzeinrichtung Semiconductor circuitry with termination impedance device |
| 04/07/2004 | EP1406388A2 Integrated circuit devices having data inversion circuits therein that reduce simultaneous switching noise and support interleaving of parallel data |
| 04/07/2004 | EP1406268A2 Integrated circuit device with automatic internal command function |
| 04/07/2004 | EP1406267A1 Semiconductor memory |
| 04/07/2004 | EP1406266A2 Magnetic memory and its write/read method |
| 04/07/2004 | EP1405315A2 Method and system for banking register file memory arrays |
| 04/07/2004 | EP1405314A2 Semiconductor device |
| 04/07/2004 | EP1405240A1 Multi input memory device reader |
| 04/07/2004 | EP1405193A2 Interface for removable storage devices |
| 04/07/2004 | CN1488176A Magnetic storage element, production method and driving method therefor, and memory array |
| 04/07/2004 | CN1488175A Spin switch and magnetic storage element using it |
| 04/07/2004 | CN1488168A Self-aligned conductive line for cross-point magnetic memory integrated circuits |
| 04/07/2004 | CN1488148A Ferroelectric memory circuit and method for its fabrication |
| 04/07/2004 | CN1488147A A method for non-destructive readout and apparatus for use with the method |
| 04/07/2004 | CN1488146A Non orthogonal MRAM device |
| 04/07/2004 | CN1488145A MRAM bit line word line architecture |
| 04/07/2004 | CN1488144A Selection device for a semiconductor memory device |
| 04/07/2004 | CN1487669A Time-delay locking loop circuit for internally correcting dutyratio and method for correcting duty cycle thereof |
| 04/07/2004 | CN1487530A Non-volatile memory |
| 04/07/2004 | CN1487529A Refresh memory unit for one phase change material storage equipment |
| 04/07/2004 | CN1487528A Data output circuit and data outputting method |
| 04/07/2004 | CN1487526A Non-volatile memory and semi-conductor integrated circuit device |
| 04/07/2004 | CN1487525A Memory equipment capable of being calibrated and calibrating method thereof |
| 04/07/2004 | CN1487524A Magnetic memory device and method |
| 04/07/2004 | CN1487523A Improved diode used in MRAM device and producing method thereof |
| 04/07/2004 | CN1145212C Semiconductor integrated circuit |
| 04/07/2004 | CN1145171C Word line control circuit |
| 04/07/2004 | CN1145170C Integrated memory with memory cells with ferroelectric memory transistors respectively |
| 04/07/2004 | CN1145169C Device for assessing unit resistances in magneto-resistance memory |
| 04/07/2004 | CN1145168C Read/write structure for magnetic-resistance random access memory |
| 04/07/2004 | CN1145167C Integrated memory with storage unit having magnetic-resistance storage effect |
| 04/07/2004 | CN1145166C Method and apparatus for compensating parasitic current consumption |
| 04/07/2004 | CN1145041C Method for detecting magnetic state of magnetic constriction zone and its application |
| 04/06/2004 | US6718430 Window-based flash memory storage system and management and access methods thereof |
| 04/06/2004 | US6717887 Semiconductor memory device having configuration for selecting desired delay locked loop clock |
| 04/06/2004 | US6717886 Control circuit for an S-DRAM |
| 04/06/2004 | US6717885 Switching circuit capable of improving memory write timing and method thereof |
| 04/06/2004 | US6717884 Synchronous memory device with reduced address pins |
| 04/06/2004 | US6717883 Semiconductor memory for logic-hybrid memory |
| 04/06/2004 | US6717880 Current reducing device in sense amplifier over driver scheme of semiconductor memory chips and its method |
| 04/06/2004 | US6717879 Semiconductor memory device requiring refresh operation |
| 04/06/2004 | US6717878 Semiconductor device |
| 04/06/2004 | US6717877 Semiconductor integration circuit device |
| 04/06/2004 | US6717875 Semiconductor memory device |
| 04/06/2004 | US6717873 Balanced sense amplifier control for open digit line architecture memory devices |
| 04/06/2004 | US6717872 Charging circuit and semiconductor memory device using the same |
| 04/06/2004 | US6717868 Semiconductor memory device and control method thereof |
| 04/06/2004 | US6717867 SRAM power-up system and method |
| 04/06/2004 | US6717866 SRAM power-up system and method |
| 04/06/2004 | US6717865 Voltage detection circuit and method for semiconductor memory devices |
| 04/06/2004 | US6717863 Transparent continuous refresh RAM cell architecture |
| 04/06/2004 | US6717848 Sensing circuit in a multi-level flash memory cell |
| 04/06/2004 | US6717847 Selective operation of a multi-state non-volatile memory system in a binary mode |
| 04/06/2004 | US6717845 Magnetic memory |
| 04/06/2004 | US6717844 Semiconductor memory device with latch circuit and two magneto-resistance elements |
| 04/06/2004 | US6717843 Polyvalent, magnetoresistive write/read memory and method for writing and reading a memory of this type |
| 04/06/2004 | US6717842 Static type semiconductor memory device with dummy memory cell |
| 04/06/2004 | US6717841 Semiconductor memory device having nonvolatile memory cell of high operating stability |
| 04/06/2004 | US6717840 Nonvolatile ferroelectric memory device |
| 04/06/2004 | US6717839 Bit-line shielding method for ferroelectric memories |
| 04/06/2004 | US6717838 Semiconductor storage device with ferroelectric capacitor and read transistor having gate communicating with bit line |
| 04/06/2004 | US6717837 Ferroelectric memory device and method of operating memory cell including ferroelectric capacitor |
| 04/06/2004 | US6717836 Method and apparatus for non-volatile memory storage |
| 04/06/2004 | US6717835 Semiconductor device |
| 04/06/2004 | US6717834 Dual bus memory controller |
| 04/06/2004 | US6717833 Semiconductor device |
| 04/06/2004 | US6717832 Method for data communication between a plurality of semiconductor modules and a controller module and semiconductor module configured for that purpose |
| 04/06/2004 | US6717780 Magnetoresistive device and/or multi-magnetoresistive device |
| 04/06/2004 | US6717777 Magnetic device with porous layer and method for manufacturing the same, and solid magnetic memory |
| 04/06/2004 | US6717460 Semiconductor device |
| 04/06/2004 | US6717447 Delay adjustment circuit |
| 04/06/2004 | US6717194 Magneto-resistive bit structure and method of manufacture therefor |
| 04/01/2004 | WO2004027872A1 Ferroelectric memory architecture |
| 04/01/2004 | WO2004027821A2 Ferroelectric transistor for storing two data bits |
| 04/01/2004 | WO2004027781A1 Refreshing of multi-port memory in integrated circuits |
| 04/01/2004 | WO2004027780A1 Semiconductor memory |
| 04/01/2004 | WO2004027779A2 Improved memory architecture |