Patents
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
04/2004
04/15/2004US20040071020 Multi-level flash EEPROM cell and method of manufacture thereof
04/15/2004US20040071019 Method of forming quantum-mechanical memory and computational devices and devices obtained thereof
04/15/2004US20040071018 Non-destructive readout
04/15/2004US20040071014 Thin-film magnetic memory device suppressing parasitic capacitance applied to data line or the like
04/15/2004US20040071013 Circuit and method for implementing a write operation with tcct-based memory cells
04/15/2004US20040071012 Method of retaining memory state in a programmable conductor RAM
04/15/2004US20040071010 Static random access memory
04/15/2004US20040071005 Memory devices, sense amplifiers, and methods of operation thereof using voltage-dependent capacitor pre-amplification
04/15/2004US20040070437 Delay adjustment circuit
04/15/2004US20040070427 Semiconductor integrated circuit device having a leakage current cutoff circuit, constructed using MT-CMOS, for reducing standby leakage current
04/15/2004US20040070026 Semiconductor integrated circuit
04/15/2004US20040070020 Nonvolatile semiconductor memory device and method for operating the same
04/15/2004US20040070008 High speed dual-port memory cell having capacitive coupling isolation and layout design
04/15/2004US20040069743 Method of fabricating an ink jet printhead chip with active and passive nozzle chamber structures
04/15/2004DE3736379B4 Gepulster Komparator hoher Verstärkung Pulsed high-gain comparator
04/15/2004DE10347467A1 Frequenzmultiplizierer und zugehöriges Multiplizierverfahren sowie Datenausgabepuffer und Halbleiterbaustein Frequency multiplier and associated multiplication method and data output buffer and semiconductor device
04/15/2004DE10347055A1 Data access method for dynamic random access memory, involves generating page mode enable signal for maintaining activated state of primary word line corresponding to primary address while activating secondary word line
04/15/2004DE10345383A1 Bankadreßabbildung gemäß einer Bankhaltezeit bei dynamischen Direktzugriffsspeichern Bankadreßabbildung according to a bank holding time in dynamic random access memories
04/15/2004DE10343525A1 Method for control of semiconductor building blocks esp. memory blocks in electronic systems, such as computer working memory, involves selecting group of semiconductor blocks
04/15/2004DE10342474A1 Anzeige der Systemoperationsfrequenz an einen DRAM während des Einschaltens Displays the system operation frequency to a DRAM during power
04/15/2004DE10341557A1 DQS-Postambel-Rauschunterdrückung durch Erzwingen einer minimalen Pulslänge DQS postamble noise reduction by enforcing a minimum pulse length
04/15/2004DE10336300A1 Delay locked loop circuit for memory device, has delay line unit with cells, delaying external clock signal, and selecting output signals of delay cells based on control signals from two control circuits
04/15/2004DE10334387A1 System und Verfahren zum Überwachen interner Spannungen auf einer integrierten Schaltung System and method for monitoring internal voltages on an integrated circuit
04/15/2004DE10323458A1 Speichersystem, das einen schnellen Prozessorbetrieb gestattet, während ein Flash-Speicher verwendet wird, bei dem kein Direktzugriff möglich ist Memory system which allows a fast processor operation while a flash memory is used in which no direct access is possible
04/15/2004DE10311824A1 Periphere Schaltkreisstruktur eines Halbleiterbauelements Peripheral circuit structure of a semiconductor device
04/15/2004DE10196802T5 Rauschunterdrückung für DRAM-Architekturen mit offener Bitleitung Noise Reduction for DRAM architectures open bit line
04/14/2004EP1408514A2 Semiconductor memory device and testing system and testing method
04/14/2004EP1408511A1 Single bit nonvolatile memory cell and methods for programming and erasing thereof
04/14/2004EP1408509A2 Random access memory device and method for driving a plate line segment therein
04/14/2004EP1407455A2 Method and apparatus for determining actual write latency and accurately aligning the start of data capture with the arrival of data at a memory device
04/14/2004EP1407449A1 Data storage medium with laterally magnetised pads and method for making same
04/14/2004EP0976133B1 Memory device and method
04/14/2004CN1489768A Non-volatile magnetic cache memory
04/14/2004CN1489767A MRAM arrangement
04/14/2004CN1489155A Semiconductor storage and control method thereof
04/14/2004CN1489154A Semiconduetor storage device based on pseudo-unit method
04/14/2004CN1489153A Semiconductor storage device having multiple-9 data input/output structure
04/14/2004CN1489152A magneto-resistance effect element and magnetic memory
04/14/2004CN1489151A Film magnetic-body storage for inhibiting stray added on dataline
04/14/2004CN1489150A Magnetic-resistance storage unit structure and magnetic-resistance random access memory circuit
04/14/2004CN1489063A Semiconductor device capable of nonvolatile transferring data at ready
04/14/2004CN1488937A Strong dielectric storage accelerated test method
04/14/2004CN1145971C Nonvolatile semiconductor memory device
04/14/2004CN1145969C Interleaved sense amplifier with single-sided precharge device
04/13/2004US6721911 Method and apparatus for testing a memory array using compressed responses
04/13/2004US6721910 Semiconductor memory improved for testing
04/13/2004US6721233 Circuit and method for reducing memory idle cycles
04/13/2004US6721232 Semiconductor device having phase error improved DLL circuit mounted thereon
04/13/2004US6721231 Semiconductor memory device, memory system and electronic instrument
04/13/2004US6721225 Semiconductor memory device with activation of a burst refresh when a long cycle is detected
04/13/2004US6721224 Memory refresh methods and circuits
04/13/2004US6721223 Semiconductor memory device
04/13/2004US6721222 Noise suppression for open bit line DRAM architectures
04/13/2004US6721221 Sense amplifier and architecture for open digit arrays
04/13/2004US6721220 Bit line control and sense amplification for TCCT-based memory cells
04/13/2004US6721217 Method for memory sensing
04/13/2004US6721214 Drive circuit and control method
04/13/2004US6721213 Electronic circuit and semiconductor storage device
04/13/2004US6721211 Voltage generator for semiconductor memory device
04/13/2004US6721210 Voltage boosting circuit for a low power semiconductor memory
04/13/2004US6721209 Semiconductor memory device
04/13/2004US6721207 Non-volatile memory system including a control device to control writing, reading and storage and output operations of non-volatile devices including memory cells and data latches
04/13/2004US6721203 Designs of reference cells for magnetic tunnel junction (MTJ) MRAM
04/13/2004US6721201 Film having structure comprising non-magnetic film between magnetic films, at least one of magnetic films being perpendicular magnetic anisotropy film including rare earth metal, iron and cobalt as main ingredients
04/13/2004US6721200 Dummy cell structure for 1T1C FeRAM cell array
04/13/2004US6721199 Nonvolatile ferroelectric memory device and method for operating main bitline load controller thereof
04/13/2004US6721198 Nonvolatile ferroelectric memory device and driving method thereof
04/13/2004US6721194 Semiconductor memory
04/13/2004US6721141 Spin-valve structure and method for making spin-valve structures
04/13/2004US6721137 Magnetoresistance device
04/13/2004US6720815 Phase adjustor for semiconductor integrated circuit
04/13/2004US6720802 Data output buffer
04/13/2004US6720628 Semiconductor device, memory system and electronic apparatus
04/13/2004US6720599 Ferroelectric memory and electronic apparatus
04/13/2004US6720597 Magnetoresistive random access memory device (mram); interconnect decreases hysteresis and stray fields created by remanent states
04/13/2004US6720596 Semiconductor device and method for driving the same
04/13/2004US6720589 Semiconductor device
04/08/2004WO2004029987A1 Method and circuitry for identifying weak bits in an mram
04/08/2004WO2004029986A1 Historical information storage for integrated circuits
04/08/2004WO2004029984A2 Non-volatile memory and its sensing method
04/08/2004WO2004029983A2 Non-volatile memory and method of programming with reduced neighboring field errors
04/08/2004WO2004029981A2 Multi-port memory cells
04/08/2004WO2004029980A2 Refresh control circuit for ics with a memory array
04/08/2004WO2004029979A1 Improved sensing of memory integrated circuits
04/08/2004WO2004029975A1 Non-volatile memory and method with reduced bit line crosstalk errors
04/08/2004WO2004029974A1 Method and apparatus for enhancing the efficiency of dynamic ram
04/08/2004WO2004029973A2 Thermally stable magnetic element utilizing spin transfer and an mram device using the magnetic element
04/08/2004WO2004029972A2 Reducing the effect of write disturbs in polymer memories
04/08/2004US20040068674 Apparatus and methods for ferroelectric ram fatigue testing
04/08/2004US20040068604 Bank address mapping according to bank retention time in dynamic random access memories
04/08/2004US20040066873 Delay locked loop circuit for internally correcting duty cycle and duty cycle correction method thereof
04/08/2004US20040066701 Method and apparatus for operating a semiconductor memory at double data transfer rate
04/08/2004US20040066698 Semiconductor memory device
04/08/2004US20040066697 Multiport memory circuit composed of 1Tr-1C memory cells
04/08/2004US20040066692 Multi-valued nonvolatile semiconductor storage
04/08/2004US20040066691 Systems and methods for communicating with memory blocks
04/08/2004US20040066688 Writing to ferroelectric memory devices
04/08/2004US20040066687 Very small swing high performance asynchronous CMOS static memory (multi-port register file) with power reducing column multiplexing scheme
04/08/2004US20040066686 Pseudostatic memory circuit
04/08/2004US20040066685 Flash memory device capable of preventing an over-erase of flash memory cells and erase method thereof