| Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008) |
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| 01/25/2005 | US6847572 Refresh control circuit and methods of operation and control of the refresh control circuit |
| 01/25/2005 | US6847571 Use of redundant memory cells to manufacture cost efficient drams with reduced self refresh current capability |
| 01/25/2005 | US6847570 Semiconductor memory having burst transfer function and internal refresh function |
| 01/25/2005 | US6847568 Sense amplifier configuration for a semiconductor memory device |
| 01/25/2005 | US6847567 Sense amplifier drive circuits responsive to predecoded column addresses and methods for operating the same |
| 01/25/2005 | US6847566 Method and circuit configuration for multiple charge recycling during refresh operations in a DRAM device |
| 01/25/2005 | US6847564 Semiconductor memory device capable of relieving defective cell |
| 01/25/2005 | US6847563 Semiconductor storage device and method for remedying defects of memory cells |
| 01/25/2005 | US6847562 Enhanced read and write methods for negative differential resistance (NDR) based memory device |
| 01/25/2005 | US6847560 Method and circuit for generating constant slew rate output signal |
| 01/25/2005 | US6847559 Input buffer circuit of a synchronous semiconductor memory device |
| 01/25/2005 | US6847555 Non-volatile semiconductor memory device reading and writing multi-value data from and into pair-cells |
| 01/25/2005 | US6847553 Techniques of recovering data from memory cells affected by field coupling with adjacent memory cells |
| 01/25/2005 | US6847550 Nonvolatile semiconductor memory having three-level memory cells and program and read mapping circuits therefor |
| 01/25/2005 | US6847549 Clock synchronized non-volatile memory device |
| 01/25/2005 | US6847548 Memory with multiple state cells and sensing method |
| 01/25/2005 | US6847547 Magnetostatically coupled magnetic elements utilizing spin transfer and an MRAM device using the magnetic element |
| 01/25/2005 | US6847545 Magnetic thin film element, memory element using the same, and method for recording and reproducing using the memory element |
| 01/25/2005 | US6847544 Magnetic memory which detects changes between first and second resistive states of memory cell |
| 01/25/2005 | US6847542 SRAM cell and integrated memory circuit using the same |
| 01/25/2005 | US6847540 Semiconductor memory device and control method thereof |
| 01/25/2005 | US6847539 Ferroelectric memory and method of reading data in the same |
| 01/25/2005 | US6847538 Double operation speed in DRAM with new memory cell configuration |
| 01/25/2005 | US6847537 Ferroelectric memory devices having a plate line control circuit and methods for operating the same |
| 01/25/2005 | US6847252 Semiconductor integrated circuit device |
| 01/25/2005 | US6847072 Low switching field magnetic element |
| 01/25/2005 | US6847047 Methods that facilitate control of memory arrays utilizing zener diode-like devices |
| 01/25/2005 | US6846703 Three-dimensional device |
| 01/25/2005 | US6846683 Method of forming surface-smoothing layer for semiconductor devices with magnetic material layers |
| 01/25/2005 | CA2294834C Electrically addressable passive device, method for electrical addressing of the same and uses of the device and the method |
| 01/25/2005 | CA2124355C Nonvolative random access memory device |
| 01/20/2005 | WO2005006376A2 Electronic device with aperture and wide lens for small emission spot size |
| 01/20/2005 | WO2005006344A1 Booster circuit |
| 01/20/2005 | WO2005006341A1 Method and apparatus for partial refreshing of drams |
| 01/20/2005 | WO2005006340A2 Sram cell structure and circuits |
| 01/20/2005 | WO2005006339A2 A scalable flash eeprom memory cell with notched floating gate and graded source region, and method of manufacturing the same |
| 01/20/2005 | WO2005006338A2 Magnetoelectronics information device having a compound magnetic free layer |
| 01/20/2005 | WO2005006337A2 Variable gate bias for a reference transistor in a non-volatile memory |
| 01/20/2005 | WO2004105039A3 STACKED 1T-nMEMORY CELL STRUCTURE |
| 01/20/2005 | US20050015640 System and method for journal recovery for multinode environments |
| 01/20/2005 | US20050015560 Method and device for masking ringing in a DDR SDRAM |
| 01/20/2005 | US20050014325 Point contact array, not circuit, and electronic circuit comprising the same |
| 01/20/2005 | US20050014297 Methods of forming magnetoresistive memory devices and assemblies |
| 01/20/2005 | US20050013186 Flash/dynamic random access memory field programmable gate array |
| 01/20/2005 | US20050013185 Dynamic random access memory with smart refresh scheduler |
| 01/20/2005 | US20050013184 Dual loop sensing scheme for resistive memory elements |
| 01/20/2005 | US20050013182 Systems and methods for sensing a memory element |
| 01/20/2005 | US20050013180 Memory circuit, display device and electronic equipment each comprising the same |
| 01/20/2005 | US20050013178 Synchronous semiconductor memory device having stable data output timing |
| 01/20/2005 | US20050013176 Circuit and method of generating a boosted voltage |
| 01/20/2005 | US20050013175 Semiconductor memory device having over-driving scheme |
| 01/20/2005 | US20050013174 System of multiplexed data lines in a dynamic random access memory |
| 01/20/2005 | US20050013173 Programming of a memory with discrete charge storage elements |
| 01/20/2005 | US20050013172 Multiple modes of operation in a cross point array |
| 01/20/2005 | US20050013171 Methods of increasing the reliability of a flash memory |
| 01/20/2005 | US20050013169 Nonvolatile semiconductor memory device |
| 01/20/2005 | US20050013167 Non-volatile multi-level, semiconductor flash memory device and method of driving same |
| 01/20/2005 | US20050013165 Flash memories with adaptive reference voltages |
| 01/20/2005 | US20050013164 Nonvolatile memory and method of driving the same |
| 01/20/2005 | US20050013163 Semiconductor memory cell, array, architecture and device, and method of operating same |
| 01/20/2005 | US20050013161 Ferroelectric memory and method of manufacturing the same |
| 01/20/2005 | US20050013160 Semiconductor memory device |
| 01/20/2005 | US20050013159 Semiconductor integrated circuit device |
| 01/20/2005 | US20050013157 Methods of reading junction-isolated depletion mode ferroelectric memory devices |
| 01/20/2005 | US20050013156 Semiconductor integrated circuit device having ferroelectric capacitor |
| 01/20/2005 | US20050013155 Method and apparatus of IC implementation based on C++ language description |
| 01/20/2005 | US20050012494 Power supply voltage lowering circuit used in semiconductor device |
| 01/20/2005 | US20050012162 Semiconductor storage device |
| 01/20/2005 | US20050012161 Semiconductor memory device |
| 01/20/2005 | US20050012157 Semiconductor device having sufficient process margin and method of forming same |
| 01/20/2005 | US20050012140 EEPROM device having selecting transistors and method of fabricating the same |
| 01/20/2005 | US20050012130 6F2 3-Transistor DRAM gain cell |
| 01/20/2005 | US20050012129 Magnetic switching element and a magnetic memory |
| 01/20/2005 | US20050012127 Via AP switching |
| 01/20/2005 | US20050012086 Programmable resistance memory element and method for making same |
| 01/20/2005 | US20050012045 Detector for alpha particle or cosmic ray |
| 01/20/2005 | DE10325757A1 Verfahren zur Herstellung von magnetischen Halbleitern mit günstigen ferromagnetischen Eigenschaften A process for producing magnetic semiconductors ferromagnetic properties with favorable |
| 01/20/2005 | DE102004029846A1 Integrated circuit memory device, has column select IO blocks and N-type sense amplifier blocks arranged in zig-zag layout pattern that spans two rows of zeroth sense amplifier region |
| 01/20/2005 | CA2529667A1 Sram cell structure and circuits |
| 01/19/2005 | EP1498952A2 Oxygen content system and method for controlling memory resistance properties |
| 01/19/2005 | EP1498904A1 Magnetic memory cell |
| 01/19/2005 | EP1498903A2 High speed data access memory arrays |
| 01/19/2005 | EP1497733A1 Destructive-read random access memory system buffered with destructive-read memory cache |
| 01/19/2005 | EP1497730A1 Methods for storing data in non-volatile memories |
| 01/19/2005 | CN1568525A Semiconductor storage device |
| 01/19/2005 | CN1568524A Semiconductor memory having mutually crossing word and bit lines, at which magnetoresistive memory cells are arranged |
| 01/19/2005 | CN1568523A Sense amplifier and architecture for open digit arrays |
| 01/19/2005 | CN1568521A Adjustable memory self-timing circuit |
| 01/19/2005 | CN1567478A Apparatus for generating refresh clock changed with capacitance of memory capacitor and method thereof |
| 01/19/2005 | CN1567477A SRAM interface compatible delayed reading/storing mode of DRAM |
| 01/19/2005 | CN1567475A Memory element with built-in error connecting function |
| 01/19/2005 | CN1185714C Semiconductor memory and its preparing process |
| 01/19/2005 | CN1185711C Semiconductor storage device |
| 01/19/2005 | CN1185630C Magnetic memory device |
| 01/19/2005 | CN1185580C Semiconductor integrated circuit and data processing system |
| 01/18/2005 | US6845459 System and method to provide tight locking for DLL and PLL with large range, and dynamic tracking of PVT variations using interleaved delay lines |
| 01/18/2005 | US6845458 System and method of operation of DLL and PLL to provide tight locking with large range, and dynamic tracking of PVT variations using interleaved delay lines |
| 01/18/2005 | US6845438 Method for controlling non-volatile semiconductor memory system by using look up table |
| 01/18/2005 | US6845433 Memory device having posted write per command |
| 01/18/2005 | US6845429 Multi-port cache memory |