Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
02/2005
02/09/2005CN1577871A Semiconductor storage device and semiconductor integrated circuit
02/09/2005CN1577869A Eeprom device having selecting transistors and method of fabricating the same
02/09/2005CN1577845A Magnetic memory device and method of manufacturing the same
02/09/2005CN1577627A 半导体记忆模块 Semiconductor memory module
02/09/2005CN1577626A Memory module integrated clock supply chip, module containing chip and operation of module
02/09/2005CN1577625A Semiconductor storage device
02/09/2005CN1577624A Semiconductor memory device capable of reducing current consumption in active mode
02/09/2005CN1577623A Data pass control device for masking write ringing in ddr sdram and method thereof
02/09/2005CN1577622A Memory circuit, display device and electronic equipment each comprising the same
02/09/2005CN1577620A 半导体存储装置 The semiconductor memory device
02/09/2005CN1577619A 磁存储装置与磁基片 A magnetic storage device and the magnetic substrate
02/09/2005CN1577618A 磁存储装置与磁基片 A magnetic storage device and the magnetic substrate
02/09/2005CN1577617A 磁存储装置与磁基片 A magnetic storage device and the magnetic substrate
02/09/2005CN1577616A Magnetic resistance type memory unit and magnetic resistance type random access storage device circuit
02/09/2005CN1577615A Magnetic storage cell and magnetic memory device using same
02/09/2005CN1577614A Magnetoresistive element, magnetic memory cell, and magnetic memory device, and method for manufacturing the same
02/09/2005CN1577612A Semiconductor memory device and module for high frequency operation
02/09/2005CN1577611A Delay locked loop (dll) circuit and method for locking clock delay by using the same
02/09/2005CN1577609A Method and memory system having mode selection between dual data strobe mode and single data strobe mode with inversion
02/09/2005CN1577608A Memory system having data inversion and data inversion method for a memory system
02/09/2005CN1577607A Amplifying circuit, amplifying apparatus, and memory apparatus
02/09/2005CN1577605A Integrated circuit memory devices including programmed memory cells and programmable and erasable memory cells
02/09/2005CN1577312A 非易失性存储器并行处理器 Nonvolatile memory parallel processor
02/09/2005CN1188864C Magnetic random access storage device
02/09/2005CN1188863C Synchronous memory module with selective clock terminal joint and memory thereof
02/08/2005US6854041 DRAM-based separate I/O memory solution for communication applications
02/08/2005US6853602 Hiding error detecting/correcting latency in dynamic random access memory (DRAM)
02/08/2005US6853601 Device and method for repairing a memory array by storing each bit in multiple memory cells in the array
02/08/2005US6853600 Ferro-electric random access memory using paraelectric and ferroelectric capacitor for generating a reference potential
02/08/2005US6853599 Magnetic memory device implementing read operation tolerant to bitline clamp voltage (VREF)
02/08/2005US6853597 Integrated circuits with parallel self-testing
02/08/2005US6853595 Semiconductor memory device
02/08/2005US6853593 Semiconductor memory device having over-driving scheme
02/08/2005US6853592 Semiconductor memory device permitting control of internal power supply voltage in packaged state
02/08/2005US6853591 Circuit and method for decreasing the required refresh rate of DRAM devices
02/08/2005US6853585 Flash memory device having uniform threshold voltage distribution and method for verifying same
02/08/2005US6853584 Circuit for compensating programming current required, depending upon programming state
02/08/2005US6853582 Nonvolatile memory with controlled voltage boosting speed
02/08/2005US6853581 Multilevel semiconductor memory, write/read method thereto/therefrom and storage medium storing write/read program
02/08/2005US6853580 Magnetoresistive element and MRAM using the same
02/08/2005US6853579 Non-refresh four-transistor memory cell
02/08/2005US6853578 Pulse driven single bit line SRAM cell
02/08/2005US6853576 Semiconductor device, method for fabricating the same, and method for driving the same
02/08/2005US6853575 Cell array of FeRAM
02/08/2005US6853317 Circuit and method for generating mode register set code
02/08/2005US6853226 Register controlled delay locked loop having an acceleration mode
02/08/2005US6853177 Semiconductor device with process monitor circuit and test method thereof
02/08/2005US6853035 Negative differential resistance (NDR) memory device with reduced soft error rate
02/08/2005US6853022 Semiconductor memory device
02/08/2005US6852578 Schottky diode static random access memory (DSRAM) device, a method for making same, and CFET based DTL
02/08/2005CA2173222C Ultra high density, non-volatile ferromagnetic random access memory
02/03/2005WO2005010998A1 Self-aligned conductive lines for fet-based magnetic random access memory devices and method of forming the same
02/03/2005WO2005010891A1 Ferroelectric and high dielectric constant integrated circuit capacitors with three-dimensional orientation for high density memories, and method of making the same
02/03/2005WO2005010889A1 Flash/dynamic random access memory field programmable gate array
02/03/2005WO2005010869A2 Method of archiving data
02/03/2005WO2005010638A2 Method and system for optimizing reliability and performance of programming data in non-volatile memory devices
02/03/2005WO2004076344A3 Nanoscopic structure and devices using the same
02/03/2005WO2004073022A3 Dram output circuitry supporting sequential data capture to reduce core access times
02/03/2005WO2004066306A3 Mram architecture with a grounded write bit line and electrically isolated read bit line
02/03/2005US20050028019 Delay locked loop with improved jitter and clock delay compensating method thereof
02/03/2005US20050026365 Nonvolatile memory cell with multiple floating gates formed after the select gate
02/03/2005US20050026336 Current limiting antifuse programming path
02/03/2005US20050026308 Magnetically lined conductors
02/03/2005US20050026307 Spin injection devices
02/03/2005US20050024985 Delay locked loop control circuit
02/03/2005US20050024984 Data input circuit and method for synchronous semiconductor memory device
02/03/2005US20050024978 Method and system for optimizing reliability and performance of programming data in non-volatile memory devices
02/03/2005US20050024974 Semiconductor memory device
02/03/2005US20050024973 Current limiting antifuse programming path
02/03/2005US20050024972 Programmable DQS preamble
02/03/2005US20050024970 Device having a memory array storing each bit in multiple memory cells
02/03/2005US20050024969 Memory controller and semiconductor comprising the same
02/03/2005US20050024965 Dynamic semiconductor storage device and method of reading and writing operations thereof
02/03/2005US20050024963 Semiconductor memory module
02/03/2005US20050024959 Semiconductor memory device capable of relieving defective cell
02/03/2005US20050024956 Column redundancy for digital multilevel nonvolatile memory
02/03/2005US20050024950 Readout circuit for semiconductor storage device
02/03/2005US20050024949 Semiconductor integrated circuit device
02/03/2005US20050024948 Semiconductor device and data processing system
02/03/2005US20050024947 Data output circuits for synchronous integrated circuit memory devices
02/03/2005US20050024944 Non-volatile semiconductor memory device adapted to store a multi-valued in a single memory cell
02/03/2005US20050024942 Semiconductor memory device having a burst continuous read function
02/03/2005US20050024941 Method of archiving data
02/03/2005US20050024940 Semiconductor memory
02/03/2005US20050024939 Detecting over programmed memory
02/03/2005US20050024938 Programming method of nonvolatile semiconductor memory device
02/03/2005US20050024936 Vertical gain cell
02/03/2005US20050024935 Thin film magnetic memory device reducing a charging time of a data line in a data read operation
02/03/2005US20050024934 Structure and method for transverse field enhancement
02/03/2005US20050024932 Method for writing data to a semiconductor memory comprising a peripheral circuit section and a memory core section including a memory cell
02/03/2005US20050024930 Magnetic memory device having yoke layer, and manufacturing method thereof
02/03/2005US20050024929 Junction-isolated depletion mode ferroelectric memory devices
02/03/2005US20050024928 Asynchronous static random access memory
02/03/2005US20050024927 Controller for processing apparatus
02/03/2005US20050024925 Configuration for generating a voltage sense signal in a power semiconductor component
02/03/2005US20050024924 1t1c sram
02/03/2005US20050024923 Gain cell memory having read cycle interlock
02/03/2005US20050024922 Read/write circuit for accessing chalcogenide non-volatile memory cells
02/03/2005US20050024920 Junction-isolated depletion mode ferroelectric memory devices
02/03/2005US20050024919 Junction-isolated depletion mode ferroelectric memory devices
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