| Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008) |
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| 02/16/2005 | CN1581490A 半导体器件和半导体存储器件 A semiconductor device and a semiconductor memory device |
| 02/16/2005 | CN1581358A Memory and its driving method |
| 02/16/2005 | CN1581356A Storage device and method for amplifying voltage level of bit line and complementary bit line |
| 02/16/2005 | CN1581355A Semiconductor device and its controlling method |
| 02/16/2005 | CN1581354A Semiconductor device |
| 02/16/2005 | CN1190012C Frequency-multiplying delay locked loop |
| 02/16/2005 | CN1189942C Semiconductor storage device, its driving method and producing method |
| 02/16/2005 | CN1189890C Semiconductor memory device with multiple low-pissipation module type |
| 02/15/2005 | US6857099 Multilevel semiconductor memory, write/read method thereto/therefrom and storage medium storing write/read program |
| 02/15/2005 | US6857055 Programmable embedded DRAM current monitor |
| 02/15/2005 | US6857054 Write-once memory storage device |
| 02/15/2005 | US6857042 Method for refreshing a dynamic memory |
| 02/15/2005 | US6856574 Semiconductor memory device |
| 02/15/2005 | US6856573 Column decoder configuration for a 1T/1C memory |
| 02/15/2005 | US6856568 Refresh operations that change address mappings in a non-volatile memory |
| 02/15/2005 | US6856567 Semiconductor device with self refresh test mode |
| 02/15/2005 | US6856566 Timer circuit and semiconductor memory incorporating the timer circuit |
| 02/15/2005 | US6856565 Thin film magnetic memory device conducting read operation by a self-reference method |
| 02/15/2005 | US6856564 Noise resistant small signal sensing circuit for a memory device |
| 02/15/2005 | US6856563 Semiconductor memory device for enhancing bitline precharge time |
| 02/15/2005 | US6856560 Redundancy in series grouped memory architecture |
| 02/15/2005 | US6856559 Semiconductor memory device |
| 02/15/2005 | US6856555 Leak immune semiconductor memory |
| 02/15/2005 | US6856551 System and method for programming cells in non-volatile integrated memory devices |
| 02/15/2005 | US6856550 Nonvolatile semiconductor memory device capable of uniformly inputting/outputting data |
| 02/15/2005 | US6856546 Multi-state memory |
| 02/15/2005 | US6856541 Segmented metal bitlines |
| 02/15/2005 | US6856539 Thin film magnetic memory device including memory cells having a magnetic tunnel junction |
| 02/15/2005 | US6856538 Thin film magnetic memory device suppressing internal magnetic noises |
| 02/15/2005 | US6856537 Thin film magnetic memory device having dummy cell |
| 02/15/2005 | US6856536 Non-volatile memory with a single transistor and resistive memory element |
| 02/15/2005 | US6856535 Reference voltage generator for ferroelectric memory |
| 02/15/2005 | US6856534 Ferroelectric memory with wide operating voltage and multi-bit storage per cell |
| 02/15/2005 | US6856532 Offset compensated sensing for magnetic random access memory |
| 02/15/2005 | US6856530 System and method to avoid voltage read errors in open digit line array dynamic random access memories |
| 02/15/2005 | US6856447 Methods and apparatus for selectively updating memory cell arrays |
| 02/15/2005 | US6856268 Control systems having an analog control unit that generates an analog value responsive to a digital value and having twice the resolution of the least significant bit of the digital value and methods of operating the same |
| 02/15/2005 | US6856031 SRAM cell with well contacts and P+ diffusion crossing to ground or N+ diffusion crossing to VDD |
| 02/15/2005 | US6856030 Semiconductor latches and SRAM devices |
| 02/15/2005 | US6855988 Semiconductor switching devices |
| 02/15/2005 | US6855977 Memory device with a self-assembled polymer film and method of making the same |
| 02/15/2005 | US6855564 Magnetic random access memory having transistor of vertical structure with writing line formed on an upper portion of the magnetic tunnel junction cell |
| 02/15/2005 | US6855264 Method of manufacture of an ink jet printer having a thermal actuator comprising an external coil spring |
| 02/10/2005 | WO2005013372A2 Spin injection devices |
| 02/10/2005 | WO2004109706A3 Nanoscale wire-based sublithographic programmable logic arrays |
| 02/10/2005 | WO2004097837A3 Method of dual cell memory device operation for improved end-of-life read margin |
| 02/10/2005 | WO2004063760A3 Magnetostatically coupled magnetic elements utilizing spin transfer and an mram device using the magnetic element |
| 02/10/2005 | US20050034093 Semiconductor integrated circuit device and method for designing the same |
| 02/10/2005 | US20050033903 Integrated circuit device |
| 02/10/2005 | US20050033901 Method and circuit for reading data from a ferroelectric memory cell |
| 02/10/2005 | US20050033899 Semiconductor memory asynchronous pipeline |
| 02/10/2005 | US20050033705 Decoy device in an integrated circuit |
| 02/10/2005 | US20050033541 Memory cell signal window testing apparatus |
| 02/10/2005 | US20050032313 Vertical gain cell |
| 02/10/2005 | US20050032277 Random access memory cell and method for fabricating same |
| 02/10/2005 | US20050030830 Magnetic random access memory |
| 02/10/2005 | US20050030829 Thin film magnetic memory device conducting data write operation by application of a magnetic field |
| 02/10/2005 | US20050030821 Magnetic memory apparatus and method of manufacturing magnetic memory apparatus |
| 02/10/2005 | US20050030819 Method and apparatus for standby power reduction in semiconductor devices |
| 02/10/2005 | US20050030818 DRAM power bus control |
| 02/10/2005 | US20050030817 Low power circuits with small voltage swing transmission, voltage regeneration, and wide bandwidth architecture |
| 02/10/2005 | US20050030816 Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell |
| 02/10/2005 | US20050030815 Semiconductor memory module |
| 02/10/2005 | US20050030813 Magnetic random access memory |
| 02/10/2005 | US20050030807 Circuit and method for refreshing memory cells of a dynamic memory |
| 02/10/2005 | US20050030806 Circuit and method for refreshing memory cells of a dynamic memory |
| 02/10/2005 | US20050030805 Memory device and method of amplifying voltage levels of bit line and complementary bit line |
| 02/10/2005 | US20050030802 Memory module including an integrated circuit device |
| 02/10/2005 | US20050030799 Logical data block, magnetic random access memory, memory module, computer system and method |
| 02/10/2005 | US20050030798 Semiconductor device and method for controlling the same |
| 02/10/2005 | US20050030793 Method for operating a nor-array memory module composed of p-type memory cells |
| 02/10/2005 | US20050030789 Method for operating a nand-array memory module composed of p-type memory cells |
| 02/10/2005 | US20050030786 Low remanence flux concentrator for MRAM devices |
| 02/10/2005 | US20050030785 Magnetic random access memory |
| 02/10/2005 | US20050030783 Dynamic RAM and semiconductor device |
| 02/10/2005 | US20050030338 Inkjet printer with low nozzle to chamber cross-section ratio |
| 02/10/2005 | US20050029920 Electron emitter device for data storage applications and method of manufacture |
| 02/10/2005 | US20050029681 Semiconductor memory device and method for producing the same |
| 02/10/2005 | US20050029664 Unitary interconnection structures integral with a dielectric layer and fabrication methods thereof |
| 02/10/2005 | US20050029565 Magnetoresistive memory devices |
| 02/10/2005 | US20050029564 Methods of forming magnetoresistive memory devices |
| 02/10/2005 | US20050029556 Compact SRAM cell with FinFET |
| 02/10/2005 | US20050029551 Semiconductor memory pipeline buffer |
| 02/10/2005 | DE10390568T5 Magnetspeicher und Verfahren zu dessen Herstellung The magnetic memory and methods for its preparation |
| 02/10/2005 | DE10345550B3 Computer memory device with several random-access memory modules divided into disjunctive module groups each having memory cells organized in disjunctive cell groups with simultaneous write-in and read-out |
| 02/10/2005 | DE10330593A1 Integrated clock-pulse supply module for memory module, has phase control loop connected to clock signal input and generating second clock signal |
| 02/10/2005 | DE10329378B3 Dynamic random-access semiconductor memory for personal digital assistant or mobile telephone has memory sub-unit with memory cell and associated pre-charge equalize circuit switched via control circuit |
| 02/10/2005 | DE10329369A1 Schaltung und Verfahren zum Auffrischen von Speicherzellen eines dynamischen Speichers Circuit and method for refreshing memory cells of a dynamic memory |
| 02/10/2005 | DE102004034760A1 System on chip memory refresh cycle controlling method for hand-held device, involves detecting temperature difference between measured and reference temperature to change refresh cycle, and applying refresh command to memory |
| 02/10/2005 | DE102004033450A1 Flash memory device e.g. non-volatile EEPROM, for storing information, has variable bit line voltage generating circuit generating variable bit line voltage changed in response to supply voltage and proportional to supply voltage |
| 02/10/2005 | DE102004033444A1 Integrierter Speicherschaltungsbaustein Integrated circuit memory block |
| 02/10/2005 | DE102004027883A1 Integrierte Speicherschaltungsbausteine und Betriebsverfahren, die ausgeführt sind, um Datenbits mit einer niedrigeren Rate in einer Testbetriebsart auszugeben An integrated circuit memory devices and operating procedures that are designed to output data bits at a lower rate in a test mode |
| 02/10/2005 | DE102004014450A1 Measuring and compensating method of skews in dual in-line memory module, involves calculating relative skew of each data transmission line with respect to slowest data transmission line |
| 02/09/2005 | EP1505607A1 Asymmetric static random access memory device having reduced bit line leakage |
| 02/09/2005 | EP1505606A2 Magnetic storage cell and magnetic memory device using same |
| 02/09/2005 | EP1504456A1 Method of manufacturing mram offset cells in a double damascene structure with a reduced number of etch steps |
| 02/09/2005 | EP1504334A1 Methods of computing with digital multistate phase change materials |
| 02/09/2005 | CN1578988A Error management for writable tracking storage units storing reference values |
| 02/09/2005 | CN1578149A Delay locked loop and method of driving the same |
| 02/09/2005 | CN1577947A Precharge apparatus in semiconductor memory device and precharge method using the same |