| Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008) |
|---|
| 01/18/2005 | US6845414 Apparatus and method of asynchronous FIFO control |
| 01/18/2005 | US6845407 Semiconductor memory device having externally controllable data input and output mode |
| 01/18/2005 | US6845347 Method for modeling an integrated circuit including a DRAM cell |
| 01/18/2005 | US6845059 High performance gain cell architecture |
| 01/18/2005 | US6845058 Serial access memory |
| 01/18/2005 | US6845056 Semiconductor memory device with reduced power consumption |
| 01/18/2005 | US6845055 Semiconductor memory capable of transitioning from a power-down state in a synchronous mode to a standby state in an asynchronous mode without setting by a control register |
| 01/18/2005 | US6845051 Semiconductor memory device and data access method for semiconductor memory device |
| 01/18/2005 | US6845050 Signal delay control circuit in a semiconductor memory device |
| 01/18/2005 | US6845049 Semiconductor memory device including a delaying circuit capable of generating a delayed signal with a substantially constant delay time |
| 01/18/2005 | US6845048 System and method for monitoring internal voltages on an integrated circuit |
| 01/18/2005 | US6845045 Background operation for memory cells |
| 01/18/2005 | US6845043 Method of verifying a semiconductor integrated circuit apparatus, which can sufficiently evaluate a reliability of a non-destructive fuse module after it is assembled |
| 01/18/2005 | US6845042 Nonvolatile semiconductor memory, fabrication method for the same, semiconductor integrated circuits and systems |
| 01/18/2005 | US6845039 Programming methods for multi-level flash EEPROMS |
| 01/18/2005 | US6845038 Magnetic tunnel junction memory device |
| 01/18/2005 | US6845037 Reference cells for TCCT based memory cells |
| 01/18/2005 | US6845036 Magnetic non-volatile memory coil layout architecture and process integration scheme |
| 01/18/2005 | US6845035 Semiconductor memory device |
| 01/18/2005 | US6845033 Structure and system-on-chip integration of a two-transistor and two-capacitor memory cell for trench technology |
| 01/18/2005 | US6845032 Non-volatile latch circuit and a driving method thereof |
| 01/18/2005 | US6845031 Nonvolatile ferroelectric memory device and method for driving the same |
| 01/18/2005 | US6845030 Nonvolatile ferroelectric memory device and method of fabricating the same |
| 01/18/2005 | US6845028 Semiconductor memory device using open data line arrangement |
| 01/18/2005 | US6844926 Semiconductor integrated circuit |
| 01/18/2005 | US6844759 Method and circuit for eliminating charge injection from transistor switches |
| 01/18/2005 | US6844754 Data bus |
| 01/18/2005 | US6844605 Magnetic memory using perpendicular magnetization film |
| 01/18/2005 | US6844583 Ferroelectric memory devices having expanded plate lines |
| 01/18/2005 | US6844204 Magnetic random access memory |
| 01/18/2005 | US6844202 High efficiency magnetic sensor for magnetic particles |
| 01/13/2005 | WO2005004165A1 Semiconductor storage device and method for reading from semiconductor storage device |
| 01/13/2005 | WO2005004164A1 Semiconductor storage device |
| 01/13/2005 | WO2005004163A1 Combination of intrinsic and shape anisotropy for reduced switching field fluctuations |
| 01/13/2005 | WO2005004162A2 Cross-point mram array with reduced voltage drop across mtj's |
| 01/13/2005 | WO2004075257A3 Memory having variable refresh control and method therefor |
| 01/13/2005 | WO2004072979A3 Mram cells having magnetic write lines with a stable magnetic state at the end regions |
| 01/13/2005 | WO2004064073A3 Spin-transfer multilayer stack containing magnetic layers with resettable magnetization |
| 01/13/2005 | WO2004049342A3 Current re-routing scheme for serial-programmed mram |
| 01/13/2005 | US20050010834 Method and apparatus for determining the write delay time of a memory |
| 01/13/2005 | US20050009270 Methods of forming memory circuitry |
| 01/13/2005 | US20050009212 Magnetoresistive random access memory devices and methods for fabricating the same |
| 01/13/2005 | US20050009210 Magnetic random access memory and method of manufacturing the same |
| 01/13/2005 | US20050007865 Method for controlling non-volatile semiconductor memory system |
| 01/13/2005 | US20050007864 Memory controller for controlling a refresh cycle of a memory and a method thereof |
| 01/13/2005 | US20050007862 Semiconductor device having mechanism capable of high-speed operation |
| 01/13/2005 | US20050007861 System for reducing row periphery power consumption in memory devices |
| 01/13/2005 | US20050007858 Method and system for reducing power when writing information to MRAM |
| 01/13/2005 | US20050007856 [power source detector] |
| 01/13/2005 | US20050007855 3-Transistor OTP ROM using CMOS gate oxide antifuse |
| 01/13/2005 | US20050007852 Method of refreshing a PCRAM memory device |
| 01/13/2005 | US20050007851 Semiconductor storage device |
| 01/13/2005 | US20050007850 Noise resistant small signal sensing circuit for a memory device |
| 01/13/2005 | US20050007849 DRAM memory circuit with sense amplifiers |
| 01/13/2005 | US20050007848 Method and system for using dynamic random access memory as cache memory |
| 01/13/2005 | US20050007847 Method and apparatus for saving current in a memory device |
| 01/13/2005 | US20050007846 Semiconductor integrated circuit device |
| 01/13/2005 | US20050007842 Amplifying circuit, amplifying apparatus, and memory apparatus |
| 01/13/2005 | US20050007839 Semiconductor switching devices |
| 01/13/2005 | US20050007836 Data strobe synchronization circuit and method for double data rate, multi-bit writes |
| 01/13/2005 | US20050007835 Integrated circuit memory devices that support selective mode register set commands and related memory modules, memory controllers, and methods |
| 01/13/2005 | US20050007834 Semiconductor memory device with current driver providing bi-directional current to data write line |
| 01/13/2005 | US20050007833 Memory cell strings |
| 01/13/2005 | US20050007831 Static random access memory device having decreased sensitivity to variations in channel physical characteristics |
| 01/13/2005 | US20050007830 System and method for reading a memory cell |
| 01/13/2005 | US20050007829 System and method for reading a memory cell |
| 01/13/2005 | US20050007825 Memory cell strings in a resistive cross point memory cell array |
| 01/13/2005 | US20050007824 Novel two-transistor flash cell for large endurance application |
| 01/13/2005 | US20050007823 Memory cell strings in a resistive cross point memory cell array |
| 01/13/2005 | US20050007822 Integrated circuit memory devices including programmed memory cells and programmable and erasable memory cells |
| 01/13/2005 | US20050007820 Variable gate bias for a reference transistor in a non-volatile memory |
| 01/13/2005 | US20050007819 Magnetic memory device and method of manufacturing the same |
| 01/13/2005 | US20050007818 Thin film magnetic memory device including memory cells having a magnetic tunnel junction |
| 01/13/2005 | US20050007816 Memory cell strings |
| 01/13/2005 | US20050007815 Magneto-resistive memory device |
| 01/13/2005 | US20050007813 Lower power and reduced device split local and continuous bitline for domino read SRAMs |
| 01/13/2005 | US20050007812 Image forming apparatus and method of forming image |
| 01/13/2005 | US20050007811 Storage device and data conversion program |
| 01/13/2005 | US20050007804 Structure and method of multiplexing bitline signals within a memory array |
| 01/13/2005 | US20050007803 Noise resistant small signal sensing circuit for a memory device |
| 01/13/2005 | US20050007801 Multi-purpose non-volatile memory card |
| 01/13/2005 | US20050007694 Magnetic field sensor utilizing anomalous hall effect magnetic film |
| 01/13/2005 | US20050007537 Thin film transistor array panel for a liquid crystal display |
| 01/13/2005 | US20050007418 Printhead assembly arrangement for a wide format pagewidth inkjet printer |
| 01/13/2005 | US20050007190 Potential generating circuit capable of correctly controlling output potential |
| 01/13/2005 | US20050007170 Asynchronous control circuit and semiconductor integrated circuit device |
| 01/13/2005 | US20050007166 Delay locked loop |
| 01/13/2005 | US20050007156 Sense amplifier and electronic apparatus using the same |
| 01/13/2005 | US20050006692 Flash memory device |
| 01/13/2005 | US20050006682 Magnetic random access memory devices having titanium-rich lower electrodes with oxide layer and oriented tunneling barrier, and methods for forming the same |
| 01/13/2005 | US20050006679 System and method for increasing magneting flux efficiency and cell density in MRAM design |
| 01/13/2005 | DE10392198T5 Erhöhen einer Auffrischperiode (Refresh Period) in einer Halbleiterspeichervorrichtung Increasing a refresh (refresh period) in a semiconductor memory device |
| 01/13/2005 | DE10361678A1 Voraufladegerät in einer Halbleiterspeichervorrichtung und Voraufladeverfahren unter Verwendung desselben Voraufladegerät thereof in a semiconductor memory device, and pre-charging using |
| 01/13/2005 | DE10339665B3 Semiconductor memory device operating method, by leaving active the cells in sub-array if access is to be made to further memory cells in same memory cell array |
| 01/13/2005 | DE102004027882A1 Multi-port memory device for video camera, has data line sense amplifiers sensing data read from memory cells of selected banks, and read data lines simultaneously transmitting data from amplifiers to buffers |
| 01/13/2005 | DE102004026526A1 Integrated circuit memory device e.g. fast cycle dynamic RAM, for use in e.g. consumer application, has write data path with N data lines connecting N switches to memory cell array to write N data bits in parallel |
| 01/12/2005 | EP1496519A2 Encoding method and memory apparatus |
| 01/12/2005 | EP1496518A1 Storage device using resistance varying storage element and reference resistance value decision method for the device |
| 01/12/2005 | EP1496424A2 Controller for information processing apparatus |
| 01/12/2005 | EP1495471A1 System and method for generating a reference voltage based on averaging the voltages of two complementary programmed dual bit reference cells |