Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
09/2005
09/21/2005CN1670859A Semiconductor memory device provided with magneto-resistive element and method for fabricating the same
09/21/2005CN1670858A Single inline memory module
09/21/2005CN1220265C Strong dielectric storage
09/21/2005CN1220216C Step-up circuit capable of converting between conventional mode and low current consumption mode and method thereof
09/21/2005CN1220215C Semiconductor storage capable of being compatible with two kinds of column address strobe waiting time at work
09/20/2005US6948029 DRAM device and refresh control method therefor
09/20/2005US6948028 Destructive-read random access memory system buffered with destructive-read memory cache
09/20/2005US6948027 Method and system for using dynamic random access memory as cache memory
09/20/2005US6947350 Synchronous controlled, self-timed local SRAM block
09/20/2005US6947349 Apparatus and method for producing an output clock pulse and output clock generator using same
09/20/2005US6947348 Gain cell memory having read cycle interlock
09/20/2005US6947347 Semiconductor memory device, and method of controlling the same
09/20/2005US6947346 Reducing digit equilibrate current during self-refresh mode
09/20/2005US6947345 Semiconductor memory device
09/20/2005US6947344 Memory device and method of reading data from a memory cell
09/20/2005US6947343 Semiconductor memory device
09/20/2005US6947342 Semiconductor storage device and information apparatus using the same
09/20/2005US6947338 Memory device
09/20/2005US6947337 Random-access memory devices comprising a dioded buffer
09/20/2005US6947336 Semiconductor device with impedance control circuit
09/20/2005US6947334 Semiconductor memory device capable of calibrating data setup time and method for driving the same
09/20/2005US6947333 Memory device
09/20/2005US6947331 Method of erasing an EEPROM cell utilizing a frequency/time domain based erased signal
09/20/2005US6947327 Nonvolatile memory and method of driving the same
09/20/2005US6947324 Logic process DRAM
09/20/2005US6947322 Semiconductor memory device
09/20/2005US6947320 Memory device capable of stable data writing
09/20/2005US6947319 Increased sensitivity in local probe of magnetic properties
09/20/2005US6947318 Magnetic random access memory
09/20/2005US6947317 Magnetic random access memory
09/20/2005US6947315 Magnetic random access memory device having write test mode
09/20/2005US6947314 Magnetic random access memory and method of manufacturing the same
09/20/2005US6947313 Method and apparatus of coupling conductors in magnetic memory
09/20/2005US6947312 MRAM having SAL layer
09/20/2005US6947310 Ferroelectric latch
09/20/2005US6947309 Ferroelectric memory device
09/20/2005US6947308 Embedded semiconductor memory with crossbar wirings and switches for high bandwidth
09/20/2005US6947264 Self-pinned in-stack bias structure for magnetoresistive read heads
09/20/2005US6946867 Data output circuit and data output method
09/20/2005US6946712 Magnetic memory device using SOI substrate
09/20/2005US6946698 MRAM device having low-k inter-metal dielectric
09/20/2005US6946697 Synthetic antiferromagnet structures for use in MTJs in MRAM technology
09/20/2005US6946302 Synthetic-ferrimagnet sense-layer for high density MRAM applications
09/20/2005US6945630 Ink jet printhead with moveable shutters
09/15/2005WO2005086250A1 Tunnel junction device
09/15/2005WO2005086171A1 Magnetic memory with a magnetic tunnel junction written in a thermally assisted manner, and method for writing the same
09/15/2005WO2005086170A1 Toggle type magnetic random access memory
09/15/2005WO2004093139B1 Memory device with sense amplifier and self-timed latch
09/15/2005WO2004073035A3 Magnetic memory elements using 360 degree domain walls
09/15/2005US20050204101 Partial dual-port memory and electronic device using the same
09/15/2005US20050204100 Flexible multi-area memory and electronic device using the same
09/15/2005US20050202855 Circuit and method for preserving data in sleep mode of semiconductor device using test scan chain
09/15/2005US20050202620 Method to manufacture polymer memory with copper ion switching species
09/15/2005US20050201255 Heating elements for a storage device
09/15/2005US20050201193 Semiconductor integrated circuit device
09/15/2005US20050201192 Memory control apparatus for synchronous memory unit with switched on/off clock signal
09/15/2005US20050201186 Semiconductor integrated circuit device
09/15/2005US20050201185 Semiconductor memory device
09/15/2005US20050201184 Semiconductor memory device with data input/output organization in multiples of nine bits
09/15/2005US20050201183 Column address path circuit and method for memory devices having a burst access mode
09/15/2005US20050201178 Method and apparatus for achieving low power consumption during power down
09/15/2005US20050201173 Method of manufacture for improved diode for use in MRAM devices
09/15/2005US20050201171 Sense amplifier and method for generating variable reference level
09/15/2005US20050201170 Semiconductor device
09/15/2005US20050201168 Semiconductor memory device
09/15/2005US20050201167 PSRAM for performing write-verify-read function
09/15/2005US20050201166 Method for screening failure of memory cell transistor
09/15/2005US20050201159 Nonvolatile semiconductor memory
09/15/2005US20050201157 Data transfer control device and electronic instrument
09/15/2005US20050201155 Memory device and fabrication method thereof
09/15/2005US20050201151 Unified multilevel cell memory
09/15/2005US20050201148 Flash memory device and architecture with multi level cells
09/15/2005US20050201147 Magnetic random access memory
09/15/2005US20050201146 Method of refreshing a PCRAM memory device
09/15/2005US20050201145 Resistive memory element sensing using averaging
09/15/2005US20050201143 Method for fabricating a semiconductor memory cell
09/15/2005US20050201142 Semiconductor integrated circuit device
09/15/2005US20050201141 Dynamic RAM storage techniques
09/15/2005US20050201140 Memory device, circuits and methods for operating a memory device
09/15/2005US20050201139 Memory Device
09/15/2005US20050201138 Nonvolatile feram control device
09/15/2005US20050201137 Ferroelectric memory device and electronic apparatus
09/15/2005US20050201136 Electrically programmable memory element with reduced area of contact and method for making same
09/15/2005US20050201023 Magnetic element utilizing spin transfer and an MRAM device using the magnetic element
09/15/2005US20050201021 Magneto-resistive effect element, magnetic sensor using magneto-resistive effect, magnetic head using magneto-resistive effect and magnetic memory
09/15/2005US20050200653 Ink distribution assembly for page width ink jet printhead
09/15/2005US20050200003 Multi-chip package
09/15/2005US20050199964 CMOS circuit including double-insulated-gate field-effect transistors
09/15/2005US20050199937 3D flash EEPROM cell and methods of implementing the same
09/15/2005US20050199927 Multiple-bit magnetic random access memory cell employing adiabatic switching
09/15/2005US20050199926 Magnetic random access memory
09/15/2005US20050199925 Magnetic random access memory
09/15/2005DE19831350B4 Halbleiterschaltungsvorrichtung, die synchron mit einem Taktsignal arbeitet, und Verfahren der Verwendung einer Halbleiterschaltungsvorrichtung, die synchron mit einem Taktsignal arbeitet A semiconductor circuit device which operates in synchronization with a clock signal, and method of using a semiconductor circuit device operating in synchronization with a clock signal
09/15/2005DE19818430B4 Bidirektionelle Datenein/Ausgabeschaltung eines Synchronspeicherelements und Verfahren zum Steuern derselben Bidirectional data input / output circuit of a synchronous memory device and method for controlling the same
09/15/2005DE19650303B4 Integrierte Speicherschaltung An integrated memory circuit
09/15/2005DE19520979B4 Spaltenredundanzvorrichtung für einen Halbleiterspeicher Column redundancy means for a semiconductor memory
09/15/2005DE10211932B4 Schaltungsanordnung zum Auslesen, Bewerten und Wiedereinlesen eines Ladungszustandes in eine Speicherzelle Circuitry for reading, evaluating and re-reading a charge state in a memory cell
09/15/2005DE102004060710A1 Data storage device for e.g. spin dependent tunneling device, has detection circuit to detect voltage change at node in response to voltage provided to memory cell string and write sense current applied across magnetic RAM cell
09/15/2005DE102004010691A1 Net based grouping method e.g. for standard cells in place and route for DRAM semiconductor chip, involves having network list with two standard cells automatically combined of standard cells out of two standard cells
09/15/2005DE102004008152B3 Halbleiterspeichervorrichtung und Verfahren zum Betreiben einer Halbleiterspeichervorrichtung A semiconductor memory device and method of operating a semiconductor memory device
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