Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
11/2013
11/27/2013CN103415886A Using low voltage regulator to supply power to a source-biased power domain
11/27/2013CN103413569A 1 read and 1 write static random access memory
11/27/2013CN102376348B Low-power dynamic random memory
11/27/2013CN102360566B Method and realization circuit for reinforcing irradiation resistance of programming points of static random access memory (SRAM)
11/27/2013CN102007543B Recording method for magnetic memory device
11/27/2013CN101894907B Method for manufacturing CuxO-based resistance memory
11/26/2013US8595591 Interference-aware assignment of programming levels in analog memory cells
11/26/2013US8595449 Memory scheduler for managing maintenance operations in a resistive memory in response to a trigger condition
11/26/2013US8593890 Implementing supply and source write assist for SRAM arrays
11/26/2013US8593879 Nonvolatile semiconductor memory device
11/26/2013US8593877 Method of programming non-volatile memory device and apparatuses for performing the method
11/26/2013US8593876 Sensing scheme in a memory device
11/26/2013US8593875 Device and method for enabling multi-value digital computation
11/26/2013US8593874 Voltage generation circuit which is capable of reducing circuit area
11/26/2013US8593872 Nonvolatile semiconductor memory device capable of speeding up data write
11/26/2013US8593867 Flash memory device and reading method thereof
11/26/2013US8593866 Systems and methods for operating multi-bank nonvolatile memory
11/26/2013US8593864 Nonvolatile memory device and method of programming the same
11/26/2013US8593863 Magnetic resistance memory apparatus having multi levels and method of driving the same
11/26/2013US8593862 Spin-transfer torque magnetic random access memory having magnetic tunnel junction with perpendicular magnetic anisotropy
11/26/2013US8593861 Asymmetric memory cells
11/26/2013US8593860 Systems and methods of sectioned bit line memory arrays
11/26/2013US8593859 Semiconductor device for preventing erroneous write to memory cell in switching operational mode between normal mode and standby mode
11/26/2013US8593858 Driving method of semiconductor device
11/26/2013US8593857 Semiconductor memory device, driving method thereof, and method for manufacturing semiconductor device
11/26/2013US8593856 Signal processing circuit and method for driving the same
11/26/2013US8593855 Semiconductor memory device
11/26/2013US8593854 Structure and method for forming conductive path in resistive random-access memory device
11/26/2013US8593853 Nonvolatile storage device and method for writing into the same
11/26/2013US8593852 Test device and test method for resistive random access memory and resistive random access memory device
11/26/2013US8593851 Verification system
11/26/2013US8592930 Magnetic memory element, magnetic memory and initializing method
11/26/2013US8592929 Symmetrically switchable spin-transfer-torque magnetoresistive device
11/26/2013CA2680752C Spin transfer torque magnetoresistive random access memory and design methods
11/21/2013WO2013173538A2 Circuit and method for controlling mram cell bias voltages
11/21/2013WO2013172066A1 Memory circuit provided with bistable circuit and non-volatile element
11/21/2013WO2013172065A1 Memory circuit
11/21/2013WO2013171947A1 Storage device, storage element
11/21/2013US20130311717 Magnetic random access memory
11/21/2013US20130308385 Apparatuses and methods for coupling load current to a common source
11/21/2013US20130308379 Semiconductor device with electrically floating body
11/21/2013US20130308376 Apparatuses including current compliance circuits and methods
11/21/2013US20130308375 Semiconductor Integrated Circuit for Low and High Voltage Operations
11/21/2013US20130308374 Circuit and method for controlling mram cell bias voltages
11/21/2013US20130308373 Nonvolatile Latch Circuit
11/21/2013US20130308372 Storage device and writing method of the same
11/21/2013US20130308367 Structure and method for forming conductive path in resistive random-access memory device
11/21/2013DE102013105049A1 Magnetischer Direktzugriffsspeicher The magnetic random access memory
11/21/2013DE102013105027A1 Optical memory system for use in e.g. computer system, has output optical transmission lines connected to electrical optical converters, where each output optical transmission line outputs electrical optical converted signal
11/20/2013EP2665104A1 Magnetoresistive elements and memory devices including the same
11/20/2013EP2399261B1 Memory architecture with a current controller and reduced power requirements
11/20/2013EP2202753B1 Information processing system with longevity evaluation
11/20/2013CN103403806A Configurable memory array
11/20/2013CN103403805A Semiconductor storage device and method for controlling same
11/20/2013CN103403804A Phase change material cell with piezoelectric or ferroelectric stress inducer liner
11/20/2013CN103400596A Writing circuit for WOx resistive random access memory
11/20/2013CN102113056B Dual power scheme in memory circuit
11/20/2013CN102057437B Semiconductor memory device
11/20/2013CN102007541B Phase change memory adaptive programming
11/20/2013CN101930793B Memory device and method for sensing and fixing margin cells
11/19/2013US8589522 Incrementally updatable system software infrastructure for sensor networks
11/19/2013US8587999 Semiconductor device
11/19/2013US8587997 Memory system to determine interference of a memory cell by adjacent memory cells, and operating method thereof
11/19/2013US8587996 Techniques for providing a direct injection semiconductor memory device
11/19/2013US8587995 Semiconductor device
11/19/2013US8587994 System and method for shared sensing MRAM
11/19/2013US8587993 Reducing source loading effect in spin torque transfer magnetoresisitive random access memory (STT-MRAM)
11/19/2013US8587992 Data-aware SRAM systems and methods forming same
11/19/2013US8587991 Recycling charges
11/19/2013US8587990 Global bit line restore by most significant bit of an address line
11/19/2013US8587988 Memory element, stacking, memory matrix and method for operation
11/19/2013US8587987 Semiconductor memory and system
11/19/2013US8587986 Variable-resistance memory device and its driving method
11/19/2013US8587985 Memory array with graded resistance lines
11/19/2013US8587984 Sensing resistance variable memory
11/19/2013US8587046 System with logic and embedded MIM capacitor
11/19/2013DE202007019569U1 Speichervorrichtung und System mit einer Speichervorrichtung Memory device and system with a memory device
11/14/2013WO2013170214A2 Resistive devices and methods of operation thereof
11/14/2013WO2013169593A2 Self referencing sense amplifier for spin torque mram
11/14/2013WO2013169526A1 Reading data from a multi - level cell memory
11/14/2013WO2013169509A1 Channel boosting using secondary neighbor channel coupling in non-volatile memory
11/14/2013WO2013169236A1 Apparatus and method for selecting memory outside a memory array
11/14/2013WO2013169235A1 Adaptive voltage input to a charge pump
11/14/2013WO2013168907A1 Semiconductor memory system and operating method for same
11/14/2013WO2013167691A1 Complementary fet injection for a floating body cell
11/14/2013WO2013071254A3 Circuit and method for generating a reference level for a magnetic random access memory element
11/14/2013US20130305079 Memory Component that Samples Command/Address Signals in Response to Both Edges of a Clock Signal
11/14/2013US20130304982 Memory device, memory system, and operating methods thereof
11/14/2013US20130303379 Hybrid superconducting-magnetic memory cell and array
11/14/2013US20130301349 Compact Semiconductor Memory Device Having Reduced Number of Contacts, Methods of Operating and Methods of Making
11/14/2013US20130301347 Shared Bit Line SMT MRAM Array with Shunting Transistors Between Bit Lines
11/14/2013US20130301346 Self referencing sense amplifier for spin torque mram
11/14/2013US20130301345 Magnetic random access memory and memory system
11/14/2013US20130301344 Multiple-port memory device comprising single-port memory device with supporting control circuitry
11/14/2013US20130301343 Threshold voltage measurement device
11/14/2013US20130301338 Hybrid resistive memory devices and methods of operating and manufacturing the same
11/14/2013US20130301337 Resistive Devices and Methods of Operation Thereof
11/14/2013US20130301336 Permutational memory cells
11/14/2013US20130301335 Architecture, system and method for testing resistive type memory
11/14/2013US20130301334 Methods, articles and devices for pulse adjustments to program a memory cell
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