Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
10/2013
10/31/2013US20130286729 Methods and Apparatus for Non-Volatile Memory Cells
10/31/2013US20130286728 Nonvolatile memory cell operating by increasing order in polycrystalline semiconductor material
10/31/2013US20130286727 Spin torque transfer memory cell structures and methods
10/31/2013US20130286724 Method, system, and device for heating a phase change memory (pcm) cell
10/31/2013US20130286723 Magnetic random access memory with field compensating layer and multi-level cell
10/31/2013US20130286722 Spin torque transfer memory cell structures and methods
10/31/2013US20130286721 Low sensing current non-volatile flip-flop
10/31/2013US20130286720 Semiconductor memory device and fabrication process thereof
10/31/2013US20130286719 Semiconductor memory with similar ram and rom cells
10/31/2013US20130286718 Methods For Reducing Power Dissipation In Drowsy Caches And For Retaining Data In Cache-Memory Sleep Mode
10/31/2013US20130286717 Implementing supply and source write assist for sram arrays
10/31/2013US20130286716 Low noise memory array
10/31/2013US20130286715 Semiconductor device with memory device
10/31/2013US20130286711 Blocking current leakage in a memory array
10/31/2013US20130286706 Memory Modules and Devices Supporting Configurable Data Widths
10/31/2013DE10246790B4 Integrierter Speicher Built-in Memory
10/31/2013DE102008034327B4 FB DRAM-Speicher mit Zustandsspeicher FB DRAM memory state memory
10/30/2013EP2657939A1 A semiconductor memory with similar RAM and ROM cells
10/30/2013CN103380462A Writable magnetic element
10/30/2013CN103378135A Apparatus for FinFETs
10/30/2013CN103377697A Method for blocking current leakage through defective memory cells in memory array
10/30/2013CN103377696A System for supplying stable voltage to storage unit
10/30/2013CN103377695A Memory systems, memory devices and memory controllers and methods for operating them
10/30/2013CN103377694A Operating method for controlling nonvolatile memory device and mapping pattern selecting method
10/30/2013CN103377692A Pre-decoder for dual power memory, and dual power memory thereof
10/30/2013CN103377685A Apparatus for SRAM cells
10/30/2013CN102324249B Bi-multi-converting circuit of embedded DRAM of K value storing unit and constructing method thereof
10/30/2013CN102290095B Storage unit circuit for any K-valued and 8-valued DRAM (dynamic random access memory)
10/30/2013CN101882464B Memory device control for self-refresh mode
10/30/2013CN101651144B Memory devices including vertical pillars and methods of manufacturing and operating same
10/29/2013US8572424 Semiconductor device to select and output data to a data bus
10/29/2013US8570814 Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell
10/29/2013US8570813 Charge pump circuit using low voltage transistors
10/29/2013US8570811 FinFET based one-time programmable device and related method
10/29/2013US8570802 Nonvolatile semiconductor memory device capable of speeding up write operation
10/29/2013US8570801 Method of programming a semiconductor memory device
10/29/2013US8570800 Memory using a plurality of diodes as program selectors with at least one being a polysilicon diode
10/29/2013US8570799 Magnetic random access memory with conversion circuitry
10/29/2013US8570798 Electronic devices formed of two or more substrates connected together, electronic systems comprising electronic devices, and methods of forming electronic devices
10/29/2013US8570797 Magnetic random access memory (MRAM) read with reduced disturb failure
10/29/2013US8570796 Nonvolatile memory cell, nonvolatile memory device and method for driving the same
10/29/2013US8570795 Adaptive wordline programming bias of a phase change memory
10/29/2013US8570794 Semiconductor memory apparatus
10/29/2013US8570793 Shared bit line SMT MRAM array with shunting transistors between bit lines
10/29/2013US8570792 Magnetoresistive random access memory
10/29/2013US8570791 Circuit and method of word line suppression
10/29/2013US8570790 Memory devices and methods for high random transaction rate
10/29/2013US8570789 SRAM timing tracking circuit
10/29/2013US8570788 Method and apparatus for power domain isolation during power down
10/29/2013US8570787 Storage apparatus and operation method for operating the same
10/29/2013US8570786 Memory device and fabricating method thereof
10/29/2013US8570785 Reading a memory element within a crossbar array
10/29/2013US8570065 Programmable LSI
10/29/2013US8569891 Forming array contacts in semiconductor memories
10/29/2013US8569852 Magnetic oscillation element and spin wave device
10/29/2013US8569835 Semiconductor device
10/29/2013US8569825 Nonvolatile semiconductor storage device
10/24/2013WO2013158958A1 Hierarchical memory magnetoresistive random-access memory (mram) architecture
10/24/2013US20130282973 Volatile memory device and a memory controller
10/24/2013US20130279284 Semiconductor memory device and method for refreshing memory cells
10/24/2013US20130279278 Memory Component with Terminated and Unterminated Signaling Inputs
10/24/2013US20130279245 Adaptive resistive device and methods thereof
10/24/2013US20130279244 Hierarchical memory magnetoresistive random-access memory (mram) architecture
10/24/2013US20130279243 Method to reduce read error rate for semiconductor resistive memory
10/24/2013US20130279242 Volatile memory elements with soft error upset immunity
10/24/2013US20130279241 Circuits and methods for reducing minimum supply for register file cells
10/24/2013US20130279236 Method and system for utilizing perovskite material for charge storage and as a dielectric
10/24/2013DE112011104526T5 Hierarchische Dram-Detektion Hierarchical dram detection
10/24/2013DE112011104523T5 NOR-Logik-Wortleitungsauswahl NOR logic-word line selection
10/24/2013DE102013100064A1 Memory device e.g. double data rate synchronous dynamic RAM, for storing boot image of e.g. mobile system, has control circuit for controlling refreshing operation of weak cell lines if decoder receives instruction to write on cell lines
10/23/2013EP2654041A2 Programmming based on controller performance requirements
10/23/2013EP2652739A2 Magnetic random access memory cells having improved size and shape characteristics
10/23/2013CN103366819A Semiconductor device and method for driving the same
10/23/2013CN103366818A Programming method of flash memory device
10/23/2013CN103366807A Dual loop sensing scheme for resistive memory elements
10/23/2013CN103366805A System and method for adjusting stopwrite threshold
10/23/2013CN103366804A Nonvolatile memory device with current injection read amplifier
10/23/2013CN103366803A Redundant-structure static random storage unit
10/23/2013CN103366802A Static random storage unit
10/23/2013CN103366801A Memory device and method of operating the same
10/23/2013CN103366800A Methods and apparatus for SRAM cell structure
10/23/2013CN103366799A Independent link and bank selection
10/23/2013CN103366798A DRAM (Dynamic Random Access Memory) and production method as well as semiconductor packaging component and packaging method
10/23/2013CN102318008B Memory architecture with current controller and reduced power requirements
10/23/2013CN102290097B Static random access memory (SRAM)
10/22/2013US8566931 Protection of information contained in an electronic circuit
10/22/2013US8565024 Sensing memory cells
10/22/2013US8565019 Method for controlling threshold value in nonvolatile semiconductor memory device
10/22/2013US8565017 Device for supplying a high erase program voltage to an integrated circuit
10/22/2013US8565016 System having improved surface planarity for bit material deposition
10/22/2013US8565015 Methods of programming two terminal memory cells
10/22/2013US8565014 Shared bit line SMT MRAM array with shunting transistors between bit lines
10/22/2013US8565013 Storage element and storage device
10/22/2013US8565012 Magnetic enhancement layer in memory cell
10/22/2013US8565011 Method of initializing magnetic memory element
10/22/2013US8565010 Magnetic random access memory with field compensating layer and multi-level cell
10/22/2013US8565009 Access to multi-port devices
10/22/2013US8565008 Method and apparatus for generating a sequence of clock signals
10/22/2013US8565007 Semiconductor memory device
10/22/2013US8565005 Nonvolatile memory element and nonvolatile memory device
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