| Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996) |
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| 10/05/1999 | US5963061 Switch for minimizing transistor exposure to high voltage |
| 10/05/1999 | US5963057 Integrated circuit |
| 10/05/1999 | US5963055 Interface circuit between different potential levels |
| 10/05/1999 | US5963054 In an integrated circuit |
| 10/05/1999 | US5963053 Self-biasing CMOS PECL receiver with wide common-mode range and multi-level-transmit to binary decoder |
| 10/05/1999 | US5963051 Segmented localized conductors for programmable logic devices |
| 10/05/1999 | US5963050 Configurable logic element with fast feedback paths |
| 10/05/1999 | US5963049 Programmable logic array integrated circuit architectures |
| 10/05/1999 | US5963047 Noise supression using neighbor-sensing for a CMOS output buffer with a large DC current sink |
| 10/05/1999 | US5962881 FPGA layout for a pair of six input multiplexers |
| 10/05/1999 | US5961576 In a field programmable integrated circuit |
| 10/05/1999 | CA2143017C Phase locked loop with improved noise rejection capability when in the locked state |
| 09/30/1999 | WO1999049577A1 Externally supplied interface adapter |
| 09/29/1999 | EP0945985A1 Semiconductor device comprising a level shifting circuit |
| 09/29/1999 | CN1229998A Semiconductor device |
| 09/28/1999 | US5959927 Semiconductor integrated circuit device having hierarchical power source arrangement |
| 09/28/1999 | US5959881 Programmable logic device including configuration data or user data memory slices |
| 09/28/1999 | US5959601 Method and apparatus for parallel in serial out transmission |
| 09/28/1999 | US5959559 Parallel-to-serial converter |
| 09/28/1999 | US5959490 High speed low voltage swing receiver for mixed supply voltage interfaces |
| 09/28/1999 | US5959489 Method and apparatus for controlling selectable functions of an external circuit |
| 09/28/1999 | US5959484 Feed back circuit |
| 09/28/1999 | US5959482 Controlled slew rate bus driver circuit having a high impedance state |
| 09/28/1999 | US5959474 Output buffer for memory circuit |
| 09/28/1999 | US5959473 Transistor output circuit |
| 09/28/1999 | US5959472 Driver circuit device |
| 09/28/1999 | US5959468 Buffer for static in/static out dynamic speed |
| 09/28/1999 | US5959466 Field programmable gate array with mask programmed input and output buffers |
| 09/28/1999 | US5959465 Fast Nor-Nor PLA operating from a single-phase clock |
| 09/28/1999 | US5958026 Input/output buffer supporting multiple I/O standards |
| 09/28/1999 | CA2145913C Apparatus for converting optical bipolar signals to optical unipolar signals |
| 09/23/1999 | WO1999048260A1 High speed signaling for interfacing vlsi cmos circuits |
| 09/23/1999 | WO1999048208A1 Circuit for reducing leaking current |
| 09/23/1999 | WO1999048004A1 Sram bus architecture and interconnect to an fpga |
| 09/23/1999 | DE19829487C1 Integrated semiconductor chip output driver e.g. with CMOS inverter-type switching stage |
| 09/23/1999 | DE19817441A1 Remotely powered interface adapter for digital data communications between the electrical interfaces of two equipments with different voltage levels for distinguishing the logic states high and low |
| 09/23/1999 | CA2323446A1 High speed signaling for interfacing vlsi cmos circuits |
| 09/22/1999 | EP0944094A2 Flash memory with improved erasability and its circuitry |
| 09/22/1999 | EP0943129A1 Unit for processing numeric and logical operations, for use in processors (cpus) and in multicomputer systems |
| 09/22/1999 | CN1229248A Voltage converting buffer circuit |
| 09/21/1999 | US5955925 Digital AGC circuit |
| 09/21/1999 | US5955913 Integrated circuit operable in a mode having extremely low power consumption |
| 09/21/1999 | US5955904 Semiconductor integrated circuit with appropriate data output timing and reduced power consumption |
| 09/21/1999 | US5955902 Frequency multiplier using a voltage controlled delay circuit |
| 09/21/1999 | US5955896 Input buffer using a differential amplifier |
| 09/21/1999 | US5955894 Method for controlling the impedance of a driver circuit |
| 09/21/1999 | US5955893 Power saving buffer circuit buffer bias voltages |
| 09/21/1999 | US5955892 Programmable integrated circuit having test antifuse circuitry for testing programming conductors |
| 09/21/1999 | US5955891 Semiconductor integrated circuit device with output circuit |
| 09/15/1999 | EP0942553A2 Oversampling type clock recovery circuit with power consumption reduced |
| 09/15/1999 | EP0942551A2 Over-sampling type clock recovery circuit using majority determination |
| 09/15/1999 | EP0942535A1 Tri-state buffers |
| 09/15/1999 | EP0942534A2 Output buffer control circuit |
| 09/15/1999 | EP0941579A1 Method and apparatus for universal program controlled bus architecture |
| 09/15/1999 | EP0650631B1 Non-disruptive, randomly addressable memory system |
| 09/15/1999 | CN1228893A Semiconductor integrated circuit for communication and battery saving method for the same |
| 09/15/1999 | CN1228885A Failsafe interface circuit |
| 09/14/1999 | US5953537 Method and apparatus for reducing the number of programmable architecture elements required for implementing a look-up table in a programmable logic device |
| 09/14/1999 | US5953262 Output circuit of a semiconductor memory device for providing an intermediate potential to an output terminal |
| 09/14/1999 | US5952875 Circuit with hot electron protection and method |
| 09/14/1999 | US5952869 High power MOS transistor |
| 09/14/1999 | US5952868 Voltage level interface circuit with set-up and hold control |
| 09/14/1999 | US5952866 CMOS output buffer protection circuit |
| 09/14/1999 | US5952856 Inductive load driving method and H-bridge circuit control device |
| 09/14/1999 | US5952852 Fast wide decode in an FPGA using probe circuit |
| 09/14/1999 | US5952851 Boosted voltage driver |
| 09/14/1999 | US5952850 Input/output circuit and a method for controlling an input/output signal |
| 09/14/1999 | US5952848 High-voltage tolerant input buffer in low-voltage technology |
| 09/14/1999 | US5952847 For an integrated circuit |
| 09/14/1999 | US5952846 Method for reducing switching noise in a programmable logic device |
| 09/14/1999 | US5952736 Pulse output circuit |
| 09/14/1999 | US5951632 Parallel signal processing circuit, semiconductor device having the circuit, and signal processing system having the circuit |
| 09/10/1999 | WO1999006845A3 Impedance control circuit |
| 09/08/1999 | EP0940920A2 Current limiting receiver with impedance/load matching for a powered down receiver chip |
| 09/08/1999 | EP0940012A1 Lookup tables which double as shift registers |
| 09/08/1999 | EP0940008A1 Amplifier with controllable output current |
| 09/08/1999 | EP0864204A4 Integrated drivers for flat panel displays employing chalcogenide logic elements |
| 09/08/1999 | EP0809888A4 A novel logic family employing two-terminal chalcogenide switches as the logic gates therein |
| 09/08/1999 | EP0720791B1 Circuit for reducing transient simultaneous conduction |
| 09/08/1999 | EP0719476B1 Buffer protection against output-node voltage excursions |
| 09/07/1999 | US5949987 Efficient in-system programming structure and method for non-volatile programmable logic devices |
| 09/07/1999 | US5949825 For reducing noise on a signal |
| 09/07/1999 | US5949721 Data output related circuit which is suitable for semiconductor memory device for high -speed operation |
| 09/07/1999 | US5949719 Field programmable memory array |
| 09/07/1999 | US5949710 Programmable interconnect junction |
| 09/07/1999 | US5949272 Bidirectional off-chip driver with receiver bypass |
| 09/07/1999 | US5949271 Bootstrap circuit suitable for buffer circuit or shift register circuit |
| 09/07/1999 | US5949270 Circuit and method of compensating for threshold value of transistor used in semiconductor circuit |
| 09/07/1999 | US5949269 Method and apparatus to reduce signal delay mismatch in a high speed interface |
| 09/07/1999 | US5949259 Zero-delay slew-rate controlled output buffer |
| 09/07/1999 | US5949254 Adjustable output driver circuit |
| 09/07/1999 | US5949253 Of a computer system |
| 09/07/1999 | US5949252 Bus configuration and input/output buffer |
| 09/07/1999 | US5949248 Apparatus and method for dynamic hardening of a digital circuit |
| 09/02/1999 | WO1999044147A2 METHOD FOR CACHEING CONFIGURATION DATA OF DATA FLOW PROCESSORS AND MODULES WITH A TWO- OR MULTIDIMENSIONAL PROGRAMMABLE CELL STRUCTURE (FPGAs, DPGAs OR SIMILAR) ACCORDING TO A HIERARCHY |
| 09/02/1999 | WO1999044120A2 METHOD FOR CONFIGURING DATA FLOW PROCESSORS AND MODULES WITH A TWO- OR MULTIDIMENSIONAL PROGRAMMABLE CELL STRUCTURE (FPGAs, DPGAs OR SIMILAR) WITHOUT PRODUCING DEADLOCKS |
| 09/02/1999 | WO1999017458A3 Two-stage multicast communication protocol |
| 09/02/1999 | CA2321877A1 Method for cacheing configuration data of data flow processors and modules with a two- or multidimensional programmable cell structure (fpgas, dpgas or similar) according to a hierarchy |
| 09/02/1999 | CA2321874A1 Method for configuring data flow processors and modules with a two- or multidimensional programmable cell structure (fpgas, dpgas or similar) without producing deadlocks |
| 09/01/1999 | EP0939490A2 Coincidence Detection Circuit |