| Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996) |
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| 01/19/1999 | US5861763 Threshold voltage scalable buffer with reference level |
| 01/19/1999 | US5861762 Inverse toggle XOR and XNOR circuit |
| 01/19/1999 | US5861761 Hierarchically connectable configurable cellular array |
| 01/19/1999 | US5861760 Programmable logic device macrocell with improved capability |
| 01/19/1999 | US5861648 Capacitor unit of a booster circuit whose low-voltage operating point margin can be expanded while an increase in area occupied thereby is suppressed |
| 01/19/1999 | US5861641 Customizable logic array device |
| 01/19/1999 | CA2025096C Method of using electronically reconfigurable gate array logic and apparatus formed thereby |
| 01/13/1999 | EP0891045A1 A coupling charge compensation device for VLSI circuits |
| 01/13/1999 | CN1204893A Interface circuit and method of setting determination level therefor |
| 01/13/1999 | CN1204886A Small amplitude signal output circuit |
| 01/13/1999 | CN1204841A OCD with low output capacitance |
| 01/12/1999 | US5859995 Method and apparatus for coordinating combinatorial logic-clocked state machines |
| 01/12/1999 | US5859800 Data holding circuit and buffer circuit |
| 01/12/1999 | US5859552 Programmable slew rate control circuit for output buffer |
| 01/12/1999 | US5859548 Charge recycling differential logic (CRDL) circuit and devices using the same |
| 01/12/1999 | US5859547 Dynamic logic circuit |
| 01/12/1999 | US5859546 Circuit and method for signal processing |
| 01/12/1999 | US5859544 Dynamic configurable elements for programmable logic devices |
| 01/12/1999 | US5859543 Programming architecture for a programmable integrated circuit employing antifuses |
| 01/12/1999 | US5859542 Programmable logic array integrated circuits with enhanced cascade |
| 01/12/1999 | US5859541 Data processor having an output terminal with selectable output impedances |
| 01/12/1999 | US5859461 Method and apparatus for interfacing integrated circuits having different supply voltages |
| 01/12/1999 | CA2136805C Diode coupled cmos logic design for quasi-static resistive dissipation with multi-output capability |
| 01/07/1999 | EP0889593A1 Programmable logic module for field programmable gate array device |
| 01/07/1999 | EP0889592A2 OCD With low output capacitance |
| 01/07/1999 | EP0889591A1 Method and corresponding circuit to prevent a parasitic transistor turn on in an output stage of an electronic circuit |
| 01/07/1999 | DE19824796A1 Logic circuit with glitch prevention for VLSI circuitry |
| 01/05/1999 | US5856951 Semiconductor memory device with an improved hierarchical power supply line configuration |
| 01/05/1999 | US5856851 Clock phase synchronizing circuit |
| 01/05/1999 | US5856752 Electronic system |
| 01/05/1999 | US5856750 Interface circuit having receiving side circuit for controlling logical threshold values |
| 01/05/1999 | US5856749 Stable output bias current circuitry and method for low-impedance CMOS output stage |
| 01/05/1999 | US5856746 Logic speed-up by selecting true/false combinations with the slowest logic signal |
| 12/30/1998 | WO1998059419A1 Forward body bias transistor circuits |
| 12/30/1998 | EP0887935A1 Noise isolation circuit |
| 12/30/1998 | CN1203706A Semi-conductor integrated circuit |
| 12/29/1998 | US5854772 Decoder circuit with less transistor elements |
| 12/29/1998 | US5854567 Low loss integrated circuit with reduced clock swing |
| 12/29/1998 | US5854561 Switched substrate bias for MOS DRAM circuits |
| 12/29/1998 | US5854560 CMOS output buffer having a high current driving capability with low noise |
| 12/24/1998 | DE19827454A1 CMOS logic circuit, e.g. inverter or NAND=gate |
| 12/23/1998 | WO1998058383A2 Electrically addressable passive device, method for electrical addressing of the same and uses of the device and the method |
| 12/23/1998 | WO1998043361A3 Iddq testable programmable logic array and a method for testing such a circuit |
| 12/23/1998 | EP0886406A1 Differential input stage for wide band reception with high common mode rejection |
| 12/23/1998 | EP0886381A1 Output logic setting circuit in semiconductor integrated circuit. |
| 12/23/1998 | EP0886380A2 Zero current draw circuit for use during a bonding option |
| 12/23/1998 | EP0886379A1 Voltage-level shifter |
| 12/23/1998 | EP0886321A1 Threshold voltage adjusting method for a MIS device and charge detecting device |
| 12/23/1998 | EP0886279A2 Address decoder, simiconductor memory and semiconductor device |
| 12/23/1998 | EP0885486A1 Threshold logic with improved signal-to-noise ratio |
| 12/23/1998 | CN2301783Y Intelligent error preventing device for power system simulation operation screen |
| 12/23/1998 | CN1202764A Level converter circuit |
| 12/23/1998 | CN1202762A Circuit device for producing digital signals |
| 12/23/1998 | CN1202734A Circuit for electrostatic discharge (ESD) protection |
| 12/22/1998 | US5852611 Module for a serial multiplex data input protection circuit |
| 12/22/1998 | US5852579 Method and circuit for preventing and/or inhibiting contention in a system employing a random access memory |
| 12/22/1998 | US5852383 Control circuit for bicmos bus drivers |
| 12/22/1998 | US5852382 Three-state CMOS output buffer circuit |
| 12/22/1998 | US5852375 5v tolerant I/O circuit |
| 12/22/1998 | US5852373 Static-dynamic logic circuit |
| 12/22/1998 | US5852372 Apparatus and method for signal handling on GTL-type buses |
| 12/22/1998 | US5852371 Voltage level translator |
| 12/22/1998 | US5852370 Integrated circuits for low power dissipation in signaling between different-voltage on chip regions |
| 12/22/1998 | US5852367 For a logic circuit |
| 12/22/1998 | US5852366 High voltage level shift circuit including CMOS transistor having thin gate insulating film |
| 12/22/1998 | US5852365 Variable logic circuit and semiconductor integrated circuit using the same |
| 12/17/1998 | DE19741178A1 FET-based logic gate with CMOS inverter |
| 12/17/1998 | DE19723539A1 Fine state machine for logical concatenation |
| 12/16/1998 | EP0884849A2 Voltage-level shifter |
| 12/16/1998 | EP0884848A1 Circuit for producing digital signals |
| 12/16/1998 | EP0884847A2 Small amplitude signal output circuit |
| 12/16/1998 | EP0884599A1 Programming mode selection with jtag circuits |
| 12/15/1998 | US5850564 Scalable multiple level tab oriented interconnect architecture |
| 12/15/1998 | US5850159 High and low speed output buffer with controlled slew rate |
| 12/15/1998 | US5850158 Ttl output stage for driving a loaf |
| 12/15/1998 | US5850155 BIMOS logic circuit directly controllable by a CMOS block formed on same IC chip |
| 12/15/1998 | US5850154 Data transmission method and data transmission circuit |
| 12/15/1998 | US5850153 Tristatable output driver for use with 3.3 or 5 volt CMOS logic |
| 12/15/1998 | US5850152 Programmable logic array integrated circuit devices |
| 12/15/1998 | US5850151 Programmable logic array intergrated circuit devices |
| 12/15/1998 | CA2117825C Fet-based optical receiver |
| 12/10/1998 | WO1998056111A1 Cmos i/o circuit with high-voltage input tolerance |
| 12/10/1998 | WO1998055928A1 Managing an information retrieval problem |
| 12/10/1998 | WO1998055918A1 Fpga with conductors segmented by active repeaters |
| 12/09/1998 | EP0883267A2 Line driver |
| 12/09/1998 | EP0883248A2 Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation |
| 12/09/1998 | EP0883247A2 Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation |
| 12/09/1998 | EP0882266A1 High-availability super server |
| 12/09/1998 | EP0882265A1 Apparatus and method for signal handling on gtl-type buses |
| 12/09/1998 | CN1201569A Logic circuits |
| 12/09/1998 | CN1201295A Multifunction power-supply control device |
| 12/08/1998 | US5848285 Macrocell having a dual purpose input register for use in a logic device |
| 12/08/1998 | US5848101 Circuits systems and methods for reducing power loss during transfer of data across an I/O bus |
| 12/08/1998 | US5848066 Methods for maximizing routability in a programmable interconnect matrix having less than full connectability |
| 12/08/1998 | US5848005 Programmable logic array integrated circuits |
| 12/08/1998 | US5847669 Semiconductor device and signal processing system using the same |
| 12/08/1998 | US5847590 Delay device and delay time measurement device using a ring oscillator |
| 12/08/1998 | US5847581 Low power CMOS precision input receiver with integrated reference |
| 12/08/1998 | US5847580 High speed bidirectional bus with multiplexers |
| 12/08/1998 | US5847579 Programmable logic array with improved interconnect structure |