Patents
Sitemap › H03 - Basic electronic circuitry › H03K - Pulse technique › H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996)
11/1999
11/03/1999CN1233885A Locking device
11/02/1999US5978827 Arithmetic processing
11/02/1999US5978826 Adder with even/odd 1-bit adder cells
11/02/1999US5978573 Logic synthesis method, semiconductor integrated circuit and arithmetic circuit
11/02/1999US5978310 Input buffer for a semiconductor memory device
11/02/1999US5978260 Method of time multiplexing a programmable logic device
11/02/1999US5977832 Method of biasing an MOS IC to operate at the zero temperature coefficient point
11/02/1999US5977819 CMOS gigabit serial link differential transmitter and receiver
11/02/1999US5977813 Temperature monitor/compensation circuit for integrated circuits
11/02/1999US5977810 Clock driver circuit and semiconductor integrated circuit device
11/02/1999US5977807 Output buffer circuit for transferring a high speed signal between large scale integrated circuits
11/02/1999US5977800 Differential MOS current-mode logic circuit having high gain and fast speed
11/02/1999US5977799 Decoding circuit for a storing circuit
11/02/1999US5977796 Low voltage differential swing interconnect buffer circuit
11/02/1999US5977795 Enhanced low voltage TTL interface
11/02/1999US5977794 Logic array having interleaved logic planes
11/02/1999US5977793 Programmable logic device with hierarchical interconnection resources
11/02/1999US5977792 Configurable logic circuit and method
11/02/1999US5977791 Embedded memory block with FIFO mode for programmable logic device
11/02/1999US5977790 Apparatus and method of providing a programmable slew rate control output driver
11/02/1999US5977789 Fast-switching logic gate
11/02/1999US5977663 Dynamic threshold gates with embedded registration
10/1999
10/28/1999WO1999055003A1 Externally supplied interface adapter
10/28/1999WO1999044147A3 METHOD FOR CACHEING CONFIGURATION DATA OF DATA FLOW PROCESSORS AND MODULES WITH A TWO- OR MULTIDIMENSIONAL PROGRAMMABLE CELL STRUCTURE (FPGAs, DPGAs OR SIMILAR) ACCORDING TO A HIERARCHY
10/27/1999EP0952668A2 Stable output buffer circuit at low slew rate
10/27/1999EP0951687A1 Programmable logic device placement method utilizing weighting function to facilitate pin locking
10/27/1999CN1233111A Over-sampling type clock recovery circuit using majority determination
10/27/1999CN1233110A Output Buffer control circuit
10/26/1999US5974476 On-chip input/output device having programmable I/O unit being configured based upon internal configuration circuit
10/26/1999US5974102 Synchronizing circuit
10/26/1999US5973900 High voltage protection for an integrated circuit input buffer
10/26/1999US5973552 Power savings technique in solid state integrated circuits
10/26/1999US5973549 Semiconductor device having input buffer with reduced bias voltage variations and low power consumption
10/26/1999US5973542 Driver circuit with temperature correction circuit
10/26/1999US5973541 Parametric tuning of an integrated circuit after fabrication
10/26/1999US5973535 Semiconductor circuit using feedback to latch multilevel data
10/26/1999US5973533 Semiconductor gate circuit having reduced dependency of input/output characteristics on power supply voltage
10/26/1999US5973530 Low power, high voltage-tolerant bus holder circuit in low voltage technology
10/26/1999US5973526 Compensating a characteristic of a circuit
10/26/1999US5973521 Semiconductor device for automatically detecting external interface voltage
10/26/1999US5973520 Output buffer circuit having a variable output impedance
10/26/1999US5973515 Differential input stage for wideband reception with high rejection of common mode
10/26/1999US5973514 1.5V bootstrapped all-N-logic true-single-phase CMOS dynamic logic circuit suitable for low supply voltage and high speed pipelined system operation
10/26/1999US5973512 CMOS output buffer having load independent slewing
10/26/1999US5973511 Voltage tolerant input/output buffer
10/26/1999US5973510 I/O interface for multilevel circuits
10/26/1999US5973509 Output buffer circuit
10/26/1999US5973508 Voltage translation circuit for mixed voltage applications
10/26/1999US5973507 Exclusive-or gate for use in delay using transmission gate circuitry
10/26/1999US5973506 Method and apparatus for connecting long lines to form wide busses
10/26/1999US5973376 Architecture having diamond shaped or parallelogram shaped cells
10/26/1999US5973345 Self-bootstrapping device
10/21/1999DE19916606A1 Converter for providing single ended output signal from differential input signal
10/21/1999DE19901185A1 NAND/NOR gate combination for operation in differential mode
10/20/1999CN1232319A Over-sampling type clock recovery circuit with power consumption reduced
10/19/1999US5970255 System for coupling programmable logic device to external circuitry which selects a logic standard and uses buffers to modify output and input signals accordingly
10/19/1999US5969999 Merged memory logic integrated circuits including buffers driven by adjustably delayed clock signals
10/19/1999US5969984 Level converting circuit for converting level of an input signal, internal potential generating circuit for generating internal potential, internal potential generating unit generating internal potential, highly reliable semiconductor device
10/19/1999US5969577 Voltage controlled oscillator less sensitive to fluctuation of threshold of component transistors
10/19/1999US5969565 Voltage booster circuit
10/19/1999US5969563 Input and output circuit with wide voltage tolerance
10/19/1999US5969562 Low noise method for interconnecting analog and digital integrated circuits
10/19/1999US5969554 Multi-function pre-driver circuit with slew rate control, tri-state operation, and level-shifting
10/19/1999US5969551 Clock generator having DLL and semiconductor device having clock generator
10/19/1999US5969544 Clock driver circuit and semiconductor integrated circuit device incorporating the clock driver circuit
10/19/1999US5969543 Input signal interface with independently controllable pull-up and pull-down circuitry
10/19/1999US5969541 Current inhibiting I/O buffer having a 5 volt tolerant input and method of inhibiting current
10/19/1999US5969540 Three-level detector without standby current
10/19/1999US5969539 Product term exporting mechanism and method improvement in an EPLD having high speed product term allocation structure
10/19/1999US5969390 Layout solution for electromagnetic interference reduction
10/14/1999WO1999052213A1 Agp/ddr interfaces for full swing and reduced swing (sstl) signals on an integrated circuit chip
10/13/1999EP0949761A1 Method and device for processing binary data
10/13/1999EP0949629A2 Semiconductor integrated circuit having a sleep mode with low power and small area
10/13/1999EP0948764A1 A microcontroller having special mode enable detection circuitry and a method of operation therefor
10/13/1999EP0855105A4 Self-configuring bus
10/13/1999EP0839409A4 Low noise tri-state output buffer
10/13/1999CN1231780A Voltage controlled variable current reference
10/13/1999CN1231547A Low power input buffer
10/13/1999CN1231546A 接口电路 Interface Circuit
10/13/1999CN1231441A Fuzzy reasoning coprocesor
10/12/1999US5966047 Programmable analog array and method
10/12/1999US5966044 Pull-up circuit and semiconductor device using the same
10/12/1999US5966041 High swing interface output stage integrated circuit for interfacing a device with a data bus
10/12/1999US5966038 Circuit with overvoltage protection
10/12/1999US5966036 System and method for a mixed voltage drive system for floating substrate technology
10/12/1999US5966035 High voltage tolerable input buffer
10/12/1999US5966032 BiCMOS transceiver (driver and receiver) for gigahertz operation
10/12/1999US5966031 Output circuit for integrated circuit devices
10/12/1999US5966030 Output buffer with regulated voltage biasing for driving voltages greater than transistor tolerance
10/12/1999US5966029 Multi-bit exclusive or
10/12/1999US5966028 Programming architecture for a programmable integrated circuit employing test antifuses and test transistors
10/12/1999US5966027 Symmetric logic block input/output scheme
10/12/1999US5964888 Circuit arrangement for executing a reset
10/06/1999EP0947049A1 Reconfiguration method for programmable components during running time
10/06/1999EP0791243B1 Cmos schmitt trigger
10/05/1999US5963107 Pulse-width modulation signal generator
10/05/1999US5963083 CMOS reference voltage generator
10/05/1999US5963075 Large scale integrated circuit having functional blocks controlled with clock signals that conduct setting operations at different times
10/05/1999US5963069 System for distributing clocks using a delay lock loop in a programmable logic circuit
10/05/1999US5963067 Reverse current throttling of a MOS transistor
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