| Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996) |
|---|
| 10/06/1998 | US5818258 Integrated circuit output buffers having duration sensitive output voltage, and related buffering methods |
| 10/06/1998 | US5818257 CMOS interface for coupling a low voltage integrated circuit with devices powered at a higher supply voltage |
| 10/06/1998 | US5818256 Low power combinational logic circuit |
| 10/06/1998 | US5818255 Method and circuit for using a function generator of a programmable logic device to implement carry logic functions |
| 10/06/1998 | US5818254 Multi-tiered hierarchical high speed switch matrix structure for very high-density complex programmable logic devices |
| 10/06/1998 | US5818253 Signal transmitting device, circuit block and integrated circuit suited to fast signal transmission |
| 10/06/1998 | US5818209 Bootstrap line power supply regulator with no filter capacitor |
| 10/01/1998 | WO1998043361A2 Iddq testable programmable logic array and a method for testing such a circuit |
| 10/01/1998 | WO1998043354A1 Fpga repeatable interconnect structure |
| 10/01/1998 | WO1998043353A1 Function block architecture for gate array |
| 10/01/1998 | WO1998029950A3 Internal voltage references output driver |
| 09/30/1998 | EP0868081A1 Clock phase synchronizing circuit |
| 09/30/1998 | EP0867071A1 A bus driver circuit configured to partially discharge a bus conductor to decrease line to line coupling capacitance |
| 09/30/1998 | CN1194702A Field programmable gate array with distributed RAM and increased cell utilization |
| 09/30/1998 | CN1194519A Demodulation method and its device, receiving method and its device, and communication device |
| 09/30/1998 | CN1194502A 半导体器件及其输入和输出电路 The semiconductor device and the input and output circuits |
| 09/30/1998 | CN1040056C 输入缓冲器 Input Buffer |
| 09/29/1998 | US5815726 Coarse-grained look-up table architecture |
| 09/29/1998 | US5815493 For use in an output module for receiving data signals |
| 09/29/1998 | US5815446 Semiconductor memory device |
| 09/29/1998 | US5815442 Data transfer apparatus with large noise margin and reduced power dissipation |
| 09/29/1998 | US5815360 Integrated circuit input/output ESD protection circuit with gate voltage regulation and parasitic zener and junction diode |
| 09/29/1998 | US5815100 Voltage multiplexed chip I/O for multi-chip modules |
| 09/29/1998 | US5815031 High density dynamic bus routing scheme |
| 09/29/1998 | US5815019 Flip-flop circuit operating on low voltage |
| 09/29/1998 | US5815015 Synchronization and shutdown circuits and methods in high-speed switching regulator drive circuits |
| 09/29/1998 | US5815013 Self back-bias compensating P-driver for multiple voltage switching environments |
| 09/29/1998 | US5815009 Process tolerant delay circuit having process sensitive and process insensitive components placed therein |
| 09/29/1998 | US5815008 Resonant tunneling diode structures for funtionally complete low-power logic |
| 09/29/1998 | US5815007 More-than-one detector |
| 09/29/1998 | US5815006 Single transition per evaluation phase latch circuit for pipelined true-single-phase synchronous logic circuit |
| 09/29/1998 | US5815005 Power reduction circuits and systems for dynamic logic gates |
| 09/29/1998 | US5815004 Multi-buffered configurable logic block output lines in a field programmable gate array |
| 09/29/1998 | US5815003 Programmable logic integrated circuits with partitioned logic element using shared lab-wide signals |
| 09/29/1998 | US5814899 SOI-type semiconductor device with variable threshold voltages |
| 09/29/1998 | CA2099171C Logic output driver |
| 09/24/1998 | WO1998042075A1 Free inverter circuit |
| 09/24/1998 | WO1998042021A1 Semiconductor integrated circuit device |
| 09/24/1998 | DE19751301A1 Schmitt-trigger circuit for input buffer |
| 09/24/1998 | DE19742162A1 Clock signal controller for data output buffer |
| 09/24/1998 | DE19738181A1 Protection circuit for integrated circuits |
| 09/24/1998 | DE19704742A1 Internes Bussystem für DFPs, sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen, zur Bewältigung großer Datenmengen mit hohem Vernetzungsaufwand Internal bus system for DFP, and modules having two or more dimensions programmable cell structures for handling large amounts of data at a high connectivity costs |
| 09/23/1998 | EP0866558A2 Programmable logic array device with random access memory configurable as product terms |
| 09/23/1998 | CN1193846A Semiconductor integrated circuits |
| 09/22/1998 | US5812595 Waveform shaping circuit for a multiplexed information bus transmitter |
| 09/22/1998 | US5812479 Programmable logic array integrated circuits |
| 09/22/1998 | US5812121 Cascode current units with inverter circuitry control |
| 09/22/1998 | US5812103 High voltage output circuit for driving gray scale flat panel displays and method therefor |
| 09/22/1998 | US5812018 Voltage booster circuit |
| 09/22/1998 | US5812015 Boosting pulse generation circuit for a semiconductor integrated circuit |
| 09/22/1998 | US5812003 TTL delay matching circuit |
| 09/22/1998 | US5811997 Multi-configurable push-pull/open-drain driver circuit |
| 09/22/1998 | US5811992 Dynamic clocked inverter latch with reduced charged leakage and reduced body effect |
| 09/22/1998 | US5811991 Logic circuit and semiconductor device using it |
| 09/22/1998 | US5811989 Programmable I/O cell with data conversion capability |
| 09/22/1998 | US5811988 PLA late signal circuitry using a specialized gap cell and PLA late signal circuitry using switched output |
| 09/22/1998 | US5811987 Block clock and initialization circuit for a complex high density PLD |
| 09/22/1998 | US5811986 Flexible synchronous/asynchronous cell structure for a high density programmable logic device |
| 09/22/1998 | US5811985 Output multiplexer circuit for input/output block |
| 09/22/1998 | US5811984 Current mode I/O for digital circuits |
| 09/22/1998 | US5811863 Transistors having dynamically adjustable characteristics |
| 09/22/1998 | US5811859 MOS inverter forming method |
| 09/17/1998 | WO1998035299A3 Method for self-synchronization of configurable elements of a programmable component |
| 09/16/1998 | EP0865164A1 Analog level conversion circuit |
| 09/16/1998 | EP0865163A1 High-voltage tolerant input buffer in low-voltage technology |
| 09/16/1998 | EP0865162A2 Optimum noise isolated I/O with minimized footprint |
| 09/16/1998 | EP0865042A2 Drive circuit, and semiconductor memory device that utilizes same |
| 09/16/1998 | EP0864204A1 Integrated drivers for flat panel displays employing chalcogenide logic elements |
| 09/16/1998 | EP0864203A1 High voltage level shifting cmos buffer |
| 09/16/1998 | EP0740861A4 Breakdown protection circuit using high voltage detection |
| 09/16/1998 | CN1193426A Glitch-free clock pulse starting circuit |
| 09/16/1998 | CN1193240A Detection-digital-signal processor in digital videl-disk reproducing device |
| 09/15/1998 | US5809281 Field programmable gate array with high speed SRAM based configurable function block configurable as high performance logic or block of SRAM |
| 09/15/1998 | US5809039 Semiconductor integrated circuit device with diagnosis function |
| 09/15/1998 | US5808942 Field programmable gate array (FPGA) having an improved configuration memory and look up table |
| 09/15/1998 | US5808897 Integrated circuit device having interchangeable terminal connection |
| 09/15/1998 | US5808490 Method and circuit for controlling a bus in system and semiconductor integrated circuit device using the same, wherein the controlling circuit comprises a latch for holding a voltage level on the bus |
| 09/15/1998 | US5808485 Clock clamping circuit that prevents clock glitching and method therefor |
| 09/15/1998 | US5808483 Logic circuit utilizing pass transistors and logic gate |
| 09/15/1998 | US5808482 For a semiconductor device |
| 09/15/1998 | US5808481 Output swing clamp for USB differential buffer |
| 09/15/1998 | US5808480 High voltage swing output buffer in low voltage technology |
| 09/15/1998 | US5808479 High speed programmable logic architecture |
| 09/15/1998 | US5808478 Digitally controlled output buffer to incrementally match line impedance and maintain slew rate independent of capacitive output loading |
| 09/15/1998 | US5808477 Circuit for detection and protection against short circuits for digital outputs |
| 09/15/1998 | US5808330 Polydirectional non-orthoginal three layer interconnect architecture |
| 09/11/1998 | WO1998039844A1 An inverse toggle xor and xnor circuit |
| 09/11/1998 | WO1998039843A1 Field programmable gate array with distributed gate-array functionality |
| 09/09/1998 | EP0863614A2 Dynamic logic circuit and self-timed pipelined datapath system |
| 09/09/1998 | EP0863515A1 Connection matrix for a semiconductor integrated microcontroller |
| 09/09/1998 | EP0862815A1 Gate oxide voltage limiting devices for digital circuits |
| 09/08/1998 | US5805912 Microprocessor arranged to synchronously access an external memory operating at a slower rate than the microproccessor |
| 09/08/1998 | US5805516 Dynamic nonvolatile memory cell |
| 09/08/1998 | US5805506 Semiconductor device having a latch circuit for latching data externally input |
| 09/08/1998 | US5805505 Circuit and method for converting a pair of input signals into a level-limited output signal |
| 09/08/1998 | US5805503 Non-disruptive randomly addressable memory system |
| 09/08/1998 | US5805477 Arithmetic cell for field programmable devices |
| 09/08/1998 | US5805438 Current controlled PWM inverter for driving a motor without gain adjustment |
| 09/08/1998 | US5805012 Systems and methods for compensating a buffer for power supply fluctuation |
| 09/08/1998 | US5805005 Voltage level converter with independently adjustable rise and fall delays |