| Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996) |
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| 01/10/2002 | US20020003437 Circuit configuration for converting logic levels |
| 01/10/2002 | US20020003436 Double data rate input and output in a programmable logic device |
| 01/10/2002 | US20020003435 Multi-functional I/O buffers in a field programmable gate array (FPGA) |
| 01/09/2002 | EP1170868A1 Field programmable gate arrays (FPGA) and method for processing FPGA configuration data |
| 01/09/2002 | EP1170867A1 Current switching logic circuit generating matched rise and fall times |
| 01/09/2002 | EP1170866A2 Comparator with duplex architecture for single event upset protection |
| 01/09/2002 | EP1170865A2 Semiconductor integrated circuit, logic operation circuit, and flip flop |
| 01/09/2002 | EP1170666A2 On-line fault tolerant operation via incremental reconfiguration of field programmable gate arrays |
| 01/09/2002 | EP1169720A1 Magnetic materials |
| 01/08/2002 | US6338157 Threshold element and method of designing the same |
| 01/08/2002 | US6338145 Input/output recovery system which is based upon an error rate and a current state of the computer environment |
| 01/08/2002 | US6337811 Semiconductor device having semiconductor element becomes operable when connected to external power source |
| 01/08/2002 | US6337586 Differential transmission driver circuit |
| 01/08/2002 | US6337584 Method and apparatus for reducing bipolar current effects in silicon-on-insulator (SOI) dynamic logic circuits |
| 01/08/2002 | US6337583 Random logic circuit |
| 01/08/2002 | US6337582 Buffer circuit |
| 01/08/2002 | US6337581 Signal transmission circuit and semiconductor memory using the same |
| 01/08/2002 | US6337580 Semiconductor integrated circuit having transistors for cutting-off subthreshold current |
| 01/08/2002 | US6337578 Redundancy circuitry for programmable logic devices with interleaved input circuits |
| 01/03/2002 | WO2002001719A2 Method and apparatus for testing high performance circuits |
| 01/03/2002 | WO2001067609A3 High speed logic family |
| 01/03/2002 | US20020001342 Carrousel handshake |
| 01/03/2002 | US20020001239 Semiconductor integrated circuit and method for controlling activation thereof |
| 01/03/2002 | US20020000889 Micropower RC oscillator |
| 01/03/2002 | US20020000873 Semiconductor device having hierarchical power supply line structure improved in operating speed |
| 01/03/2002 | US20020000865 Semiconductor integrated circuit device |
| 01/03/2002 | US20020000864 Semiconductor integrated circuit device using substrate bising and device control method thereof |
| 01/03/2002 | US20020000849 Input buffer having dual paths |
| 01/03/2002 | US20020000848 Bus driver circuit |
| 01/03/2002 | US20020000847 Signal transmission with reduced ringing of signals |
| 01/03/2002 | US20020000845 Complementary current mode driver for high speed data communications |
| 01/03/2002 | US20020000843 Input Buffer Circuit For RF Phase-Locked Loops |
| 01/03/2002 | US20020000835 Path transistor circuit and method for designing the same, a device and method for optimizing logic circuits, and a computer product |
| 01/03/2002 | US20020000834 Semiconductor logic circuit device of low current consumption |
| 01/03/2002 | US20020000832 Programmable circuit with preview function |
| 01/03/2002 | US20020000830 Noise-resistant output stage circuit |
| 01/03/2002 | US20020000827 Semiconductor integrated circuit device |
| 01/03/2002 | CA2410432A1 Method and apparatus for testing high performance circuits |
| 01/02/2002 | EP1168804A2 Inductive coupling for silicon data access arrangement |
| 01/02/2002 | EP1168625A2 Logic circuit |
| 01/02/2002 | EP1168624A2 CMOS bus driver circuit |
| 01/02/2002 | EP1168365A2 Negative-voltage bias circuit |
| 01/02/2002 | EP1168362A2 Flash memory with improved erasability and its circuitry |
| 01/02/2002 | EP1168353A2 Slew tolerant clock input buffer |
| 01/02/2002 | EP1168178A2 Logic circuit having error detection function, redundant resource management method, and fault tolerant system using it |
| 01/02/2002 | EP1166443A2 Single rail domino logic for four-phase clocking scheme |
| 01/02/2002 | CN1329396A Semiconductor IC, logical calculus circuit and trigger |
| 01/01/2002 | US6336195 Method for debugging keyboard basic input/output system (KB-BIOS) in a development notebook computing system |
| 01/01/2002 | US6335885 Semiconductor device having a delay circuit for adjusting the timing of control signals |
| 01/01/2002 | US6335653 Transmission gate |
| 01/01/2002 | US6335650 Method and apparatus for adjusting time delays in circuits with multiple operating supply voltages |
| 01/01/2002 | US6335648 Circuit using internal pull-up/pull-down resistor during reset |
| 01/01/2002 | US6335645 Semiconductor integrated circuit having built-in self-test circuit |
| 01/01/2002 | US6335639 Non-monotonic dynamic exclusive-OR/NOR gate circuit |
| 01/01/2002 | US6335637 Two-supply protection circuit |
| 01/01/2002 | US6335634 Circuitry and methods for internal interconnection of programmable logic devices |
| 01/01/2002 | US6335633 Adjustable, full CMOS input buffer for TTL, CMOS, or low swing input protocols |
| 01/01/2002 | US6335632 CMOS small signal switchable terminator network |
| 01/01/2002 | US6335616 Ringing preventive circuit, device under test board, pin electronics card, and semiconductor device |
| 01/01/2002 | CA2223221C Circuit for easily testing a logic circuit having a number of input-output pins by scan path |
| 12/27/2001 | WO2001055821A3 Microprocessor resistant to power analysis |
| 12/27/2001 | US20010056570 Methods for configuring FPGA's having variable grain blocks and shared logic for providing symmetric routing of result output to differently-directed and tristateable interconnect resources |
| 12/27/2001 | US20010056558 Configuration memory integrated circuit |
| 12/27/2001 | US20010055357 Clock signal selection system, method of generating a clock signal and programmable clock manager including same |
| 12/27/2001 | US20010054999 Level shifter |
| 12/27/2001 | US20010054924 Logic circuit having phase-controlled data receiving interface |
| 12/27/2001 | US20010054917 Driver circuit, receiver circuit, and semiconductor integrated circuit device |
| 12/27/2001 | US20010054916 Logic circuit and its forming method |
| 12/27/2001 | US20010054915 Semiconductor integrated circuit |
| 12/27/2001 | US20010054914 Integrated circuit device including CMOS tri-state drivers suitable for powerdown |
| 12/27/2001 | US20010054886 Input circuit and output circuit |
| 12/25/2001 | US6334208 Method and apparatus for in-system programming with a status bit |
| 12/25/2001 | US6334136 Dynamic 3-level partial result merge adder |
| 12/25/2001 | US6334120 Semiconductor arithmetic circuit and data processing device |
| 12/25/2001 | US6334084 Fail-safe apparatus and fail-safe method for electronic control system |
| 12/25/2001 | US6333875 Semiconductor circuit with adjustment of double data rate data latch timings |
| 12/25/2001 | US6333709 Analog to digital converter using remainder feedback loop |
| 12/25/2001 | US6333672 Differential logic circuit and method of use |
| 12/25/2001 | US6333668 Semiconductor device for suppressing current peak flowing to/from an external power supply |
| 12/25/2001 | US6333663 High voltage tolerant interface circuit |
| 12/25/2001 | US6333662 Latch type level shift circuit |
| 12/25/2001 | US6333656 Flip-flops |
| 12/25/2001 | US6333654 Variable power supply technique for use with a high efficiency line driver |
| 12/25/2001 | US6333645 Clocked logic gate circuit |
| 12/25/2001 | US6333643 Hotplug tolerant I/O circuit |
| 12/25/2001 | US6333642 Level converting method and circuit having an intermediate voltage level range and a clamping circuit |
| 12/25/2001 | US6333641 Apparatus and methods for dynamically defining variably sized autonomous sub-arrays within a programmable gate array |
| 12/25/2001 | US6333640 Asynchronous logic with intermediate value between data and null values |
| 12/25/2001 | US6333639 Method and apparatus for independent output driver calibration |
| 12/25/2001 | US6333571 MOS integrated circuit device operating with low power consumption |
| 12/20/2001 | WO2001097382A1 Configurable cell for customizable logic array device |
| 12/20/2001 | WO2001097381A1 Non-volatile reprogrammable logic circuits by combining negative differential resistance devices and magnetic devices |
| 12/20/2001 | WO2001097380A1 Apparatus and circuit having reduced leakage current and method therefor |
| 12/20/2001 | WO2001097289A1 Silicon on insulator logic circuit utilizing diode switching elements |
| 12/20/2001 | WO2001097288A1 Semiconductor device for preventing noise generation |
| 12/20/2001 | WO2001056155A3 Mixed swing voltage repeaters for high resistance or high capacitance signal lines and methods therefor |
| 12/20/2001 | US20010052819 Buffer circuit comprising load, follower transistor and current source connected in series |
| 12/20/2001 | US20010052800 Semiconductor integrated circuit device |
| 12/20/2001 | US20010052799 Low noise logic gate |
| 12/20/2001 | US20010052797 Data driven keeper for a domino circuit |