| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 05/05/1994 | DE4336887A1 Integrated semiconductor circuit e.g. DRAM chip - has distance between second output device - with drive rate adjusting element - and potential contact, greater than distance between first device and contact |
| 05/05/1994 | DE4336884A1 Semiconductor device with predetermined test mode - applies potential at pre-specified internal node to external contact in test mode in response to control signals |
| 05/05/1994 | DE4336866A1 Thin-film FET on insulator for static RAM - has crystal-structure channel region providing source-drain current control for given channel width |
| 05/05/1994 | DE4327290A1 Master-slice type integrated circuit - has several semiconductor regions which are mutually insulated, set in first longitudinal direction, and connected to several supply lines |
| 05/05/1994 | DE4318660A1 DRAM with capacitor structure - has semiconductor substrate and doped region of opposite conductivity and insulating layer on substrate surface with aperture reaching to doped layer |
| 05/05/1994 | DE4314301C1 Surface scanning sensor - has a sensor point of a photo-structurable glass |
| 05/05/1994 | DE4301915A1 Multi-chip package semiconductor device - has conductive frame for semiconductor chips with several conductors and cross-conductors |
| 05/05/1994 | DE4236750A1 Suppression of nucleus formation on insulating layers used as a mask - by adsorbing particles of layer source and removing from surface during CVD semiconductor layer formation |
| 05/05/1994 | DE4236609A1 Method for forming a structure in the surface of a substrate - with an auxiliary structure laterally bounding an initial masking structure, followed by selective removal of masking structure using the auxiliary structure as an etching mask |
| 05/04/1994 | EP0595775A1 Method of evaluating the dielectric layer of nonvolatile EPROM, EEPROM and flash-EEPROM memories |
| 05/04/1994 | EP0595750A1 An alternating RIM phase-shifting mask. |
| 05/04/1994 | EP0595749A2 In situ resist control during spray and spin in vapor |
| 05/04/1994 | EP0595652A1 Method and apparatus for detecting wire bond pull test failure modes |
| 05/04/1994 | EP0595629A1 Trimming circuit |
| 05/04/1994 | EP0595624A1 Film forming apparatus for filling fine pores of a substrate |
| 05/04/1994 | EP0595484A1 NMOS LDD PMOS HALO IC process for CMOS transistors |
| 05/04/1994 | EP0595481A1 Method of diffusing impurities into sidewalls of semiconductor structures from a doped SOG layer |
| 05/04/1994 | EP0595464A2 Method for growing oxide layers in an integreted circuit fabrication process |
| 05/04/1994 | EP0595404A2 A current sensing circuit |
| 05/04/1994 | EP0595360A1 Method of manufacturing a semiconductor device having a cylindrical electrode |
| 05/04/1994 | EP0595355A1 Semiconductor device with a protection element and method for manufacturing the same |
| 05/04/1994 | EP0595307A2 Clamp ring and processing chamber comprising said clamp ring |
| 05/04/1994 | EP0595300A1 Apparatus for manufacturing semiconductor device |
| 05/04/1994 | EP0595298A1 A semiconductor device having a hollow around a gate electrode and a method for producing the same |
| 05/04/1994 | EP0595250A2 Method of fabricating non-volatile semiconductor memory device |
| 05/04/1994 | EP0595233A2 Method for constructing semiconductor-on-insulator |
| 05/04/1994 | EP0595196A1 Optical focus test pattern monitoring system and process |
| 05/04/1994 | EP0595115A1 Process of producing chalcopyrite-type compound thin film |
| 05/04/1994 | EP0595107A2 Sensor arrangement for recording finger prints and process for their manufacturing |
| 05/04/1994 | EP0595071A1 Wafer holding apparatus for holding a wafer |
| 05/04/1994 | EP0595054A1 Method for processing semiconductor wafers at temperatures exceeding 400 degrees C. |
| 05/04/1994 | EP0595053A2 Anisotropic liquid phase photochemical etch method |
| 05/04/1994 | EP0595021A1 Improved lead frame package for electronic devices |
| 05/04/1994 | EP0595020A2 Process control for submicron linewidth measurement |
| 05/04/1994 | EP0594994A2 Semiconductor diamond and process for producing the same |
| 05/04/1994 | EP0594978A2 Method for producing a field effect transistor |
| 05/04/1994 | EP0594920A1 Method of evaluating the gate oxide of non-volatile EPROM, EEPROM and flash-EEPROM memories |
| 05/04/1994 | EP0594654A1 Machine tool with curved drive, especially for stamping and shaping the connecting pins of integrated circuits. |
| 05/04/1994 | EP0594652A1 Machine tool with curved drive, especially for stamping and shaping the connecting pins of integrated circuits. |
| 05/04/1994 | EP0424464B1 Thermally stable phenolic resin compositions and their use in light-sensitive compositions |
| 05/03/1994 | USRE34598 Integrated circuit |
| 05/03/1994 | US5309402 Flash electrically erasable and programmable ROM |
| 05/03/1994 | US5309401 Static memory device |
| 05/03/1994 | US5309392 Semiconductor IC device using ferroelectric material in data storage cells with light assisted state transition |
| 05/03/1994 | US5309354 Electron beam exposure method |
| 05/03/1994 | US5309240 CCD linear image sensor including a CCD shift register on both sides of linearly arranged photosensor cells |
| 05/03/1994 | US5309197 Projection exposure apparatus |
| 05/03/1994 | US5309090 Apparatus for heating and controlling temperature in an integrated circuit chip |
| 05/03/1994 | US5309088 Measurement of semiconductor parameters at cryogenic temperatures using a spring contact probe |
| 05/03/1994 | US5309049 Alternating current magnetic levitation transport system |
| 05/03/1994 | US5309043 Compound logic circuit having NAND and NOR gate outputs and two transistors connected within both gate circuits |
| 05/03/1994 | US5309027 Encapsulated semiconductor package having protectant circular insulators |
| 05/03/1994 | US5309025 Semiconductor bond pad structure and method |
| 05/03/1994 | US5309023 Contact structure for interconnection in semiconductor devices and manufacturing method thereof |
| 05/03/1994 | US5309022 Ni-Ge-Au ohmic contacts for GaAs and GaAlAs |
| 05/03/1994 | US5309021 Semiconductor device having particular power distribution interconnection arrangement |
| 05/03/1994 | US5309016 Semiconductor integrated circuit device having terminal members provided between semiconductor element and leads |
| 05/03/1994 | US5309015 Clock wiring and semiconductor integrated circuit device having the same |
| 05/03/1994 | US5309013 Photoelectric conversion device |
| 05/03/1994 | US5309010 Semiconductor device having improved thin film transistors |
| 05/03/1994 | US5309008 Semiconductor memory device having a trench capacitor |
| 05/03/1994 | US5309005 Charge transfer device having a bent transfer channel |
| 05/03/1994 | US5309003 Article comprising a real space transfer semiconductor device, and method of making the article |
| 05/03/1994 | US5309002 Semiconductor device with protruding portion |
| 05/03/1994 | US5309000 Electronic operating at a high temperature |
| 05/03/1994 | US5308998 Insulated gate field effect semiconductor devices having a LDD region and an anodic oxide film of a gate electrode |
| 05/03/1994 | US5308997 Self-aligned thin film transistor |
| 05/03/1994 | US5308993 Semiconductor wafer cassette mapper having dual vertical column of light emitting apertures and a single vertical column of light receiving apertures |
| 05/03/1994 | US5308989 Fluid flow control method and apparatus for an ion implanter |
| 05/03/1994 | US5308980 Thermal mismatch accommodated infrared detector hybrid array |
| 05/03/1994 | US5308955 Vertical heat treatment apparatus with vented heat insulation cover means |
| 05/03/1994 | US5308950 Method of removing material from a surface in a vacuum chamber |
| 05/03/1994 | US5308929 Multilayer structure |
| 05/03/1994 | US5308927 Wiring board and a method of manufacturing |
| 05/03/1994 | US5308796 Using silicide as catalyst for selective plating |
| 05/03/1994 | US5308794 Aluminum-germanium alloys for VLSI metallization |
| 05/03/1994 | US5308793 Oxidation resistant protective coating |
| 05/03/1994 | US5308792 Method for fabricating semiconductor device |
| 05/03/1994 | US5308791 Cleaning, oxide decomposition |
| 05/03/1994 | US5308790 Selective sidewall diffusion process using doped SOG |
| 05/03/1994 | US5308789 Method of preparing diffused silicon device substrate |
| 05/03/1994 | US5308788 Temperature controlled process for the epitaxial growth of a film of material |
| 05/03/1994 | US5308787 Uniform field oxidation for locos isolation |
| 05/03/1994 | US5308786 Trench isolation for both large and small areas by means of silicon nodules after metal etching |
| 05/03/1994 | US5308785 Isolation technique for silicon germanium devices |
| 05/03/1994 | US5308784 Isolation of electrical elements by using trenches, refilling |
| 05/03/1994 | US5308783 Process for the manufacture of a high density cell array of gain memory cells |
| 05/03/1994 | US5308782 Forming a vertical static random access memory cell using overlying thin film resistors and isolated electrodes acting as capacitors |
| 05/03/1994 | US5308781 High speed |
| 05/03/1994 | US5308780 Surface counter-doped N-LDD for high hot carrier reliability |
| 05/03/1994 | US5308779 High resolution |
| 05/03/1994 | US5308778 Method of formation of transistor and logic gates |
| 05/03/1994 | US5308777 Doping into center part of channel area to enhance programming and prevent encroachment of P+ layer upon N+ source/drain junction |
| 05/03/1994 | US5308776 Method of manufacturing SOI semiconductor device |
| 05/03/1994 | US5308745 Alkaline-containing photoresist stripping compositions producing reduced metal corrosion with cross-linked or hardened resist resins |
| 05/03/1994 | US5308744 Light sensitive elements, relief images and photoresists |
| 05/03/1994 | US5308742 Method of etching anti-reflection coating |
| 05/03/1994 | US5308722 Voting technique for the manufacture of defect-free printing phase shift lithography |
| 05/03/1994 | US5308721 Self-aligned method of making phase-shifting lithograhic masks having three or more phase-shifts |
| 05/03/1994 | US5308686 Substrate having a multiple metal protected conductive layer and method of manufacturing the same |