Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
02/2004
02/05/2004US20040024482 Engineered thermal management devices and methods of the same
02/05/2004US20040024164 Siloxane-based resin and method for forming insulating film between interconnect layuers in semiconductor devices by using the same
02/05/2004US20040023610 Polishing article for processing a substrate comprises a fabric layer having a conductive layer disposed thereover. The conductive layer has an exposed surface adapted to polish a substrate. The fabric layer may be woven or non-woven. The
02/05/2004US20040023609 Wafer holding ring for checmial and mechanical polisher
02/05/2004US20040023607 Method and apparatus for integrated chemical mechanical polishing of copper and barrier layers
02/05/2004US20040023602 Chemical mechanical polishing and pad dressing method
02/05/2004US20040023519 Single molecule array on silicon substrate for quantum computer
02/05/2004US20040023518 Method for manufacturing silicon wafer
02/05/2004US20040023517 Wafer batch processing system having processing tube
02/05/2004US20040023516 Passivation method for improved uniformity and repeatability for atomic layer deposition and chemical vapor deposition
02/05/2004US20040023515 Adhesion of carbon doped oxides by silanization
02/05/2004US20040023514 Method of manufacturing carbon nonotube semiconductor device
02/05/2004US20040023513 Method for manufacturing semiconductor device, substrate treater, and substrate treatment system
02/05/2004US20040023512 Method of forming multiple oxide layers with different thicknesses in a linear nitrogen doping process
02/05/2004US20040023511 Low temperature dielectric deposition to improve copper electromigration performance
02/05/2004US20040023510 Method for producing a quartz glass tank for use in ultrasonic cleaning used for fabricating semiconductor and quartz glass tank obtainable from that method
02/05/2004US20040023509 Electron beam mask substrate, electron beam mask blank, electron beam mask, and fabrication method thereof
02/05/2004US20040023508 Method of plasma etching a deeply recessed feature in a substrate using a plasma source gas modulated etchant system
02/05/2004US20040023507 Processing method
02/05/2004US20040023506 Method of blocking nitrogen from thick gate oxide during dual gate CMP
02/05/2004US20040023505 Method of removing ALF defects after pad etching process
02/05/2004US20040023504 Hot plate annealing
02/05/2004US20040023503 Technique for elimination of pitting on silicon substrate during gate stack etch
02/05/2004US20040023502 Undoped and fluorinated amorphous carbon film as pattern mask for metal etch
02/05/2004US20040023501 Method of removing HDP oxide deposition
02/05/2004US20040023500 Method for blocking implants from the gate of an electronic device via planarizing films
02/05/2004US20040023499 Method of manufacturing multi-level contacts by sizing of contact sizes in integrated circuits
02/05/2004US20040023497 Method for avoiding carbon and nitrogen contamination of a dielectric insulating layer
02/05/2004US20040023496 CMP slurry compositions for oxide films and methods for forming metal line contact plugs using the same
02/05/2004US20040023495 Contacts for electrochemical processing
02/05/2004US20040023494 Selective treatment of microelectronic workpiece surfaces
02/05/2004US20040023493 Isolating method and transferring method for semiconductor devices
02/05/2004US20040023492 Method for planarizing metal interconnects
02/05/2004US20040023491 Preparation and use of an abrasive slurry composition
02/05/2004US20040023490 Method of controlling the chemical mechanical polishing of stacked layers having a surface topology
02/05/2004US20040023489 Method of controlling metal formation processes using ion implantation, and system for performing same
02/05/2004US20040023488 Integrated circuit trenched features and method of producing same
02/05/2004US20040023486 Method of implantation after copper seed deposition
02/05/2004US20040023485 Method for preventing cracking and improving barrier layer adhesion in multi- layered low-k semiconductor devices
02/05/2004US20040023484 Method of deep contact fill and planarization for dual damascene structures
02/05/2004US20040023483 Manufacturing method of semiconductor device
02/05/2004US20040023482 Method for adjusting an electrical parameter on an integrated electronic component
02/05/2004US20040023481 Electrolytic contact pads
02/05/2004US20040023480 Semiconductor processing methods, and semiconductor assemblies
02/05/2004US20040023479 Method of making a molecule-surface interface
02/05/2004US20040023478 Capped dual metal gate transistors for CMOS process and method for making the same
02/05/2004US20040023477 Selective etching of polysilicon
02/05/2004US20040023476 Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size
02/05/2004US20040023475 Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication
02/05/2004US20040023474 Silicon rich barrier layers for integrated circuit devices
02/05/2004US20040023473 METHOD OF FABRICATING A PATTERNED SOI EMBEDDED DRAM/eDRAM HAVING A VERTICAL DEVICE CELL AND DEVICE FORMED THEREBY
02/05/2004US20040023472 Method for fabricating semiconductor device
02/05/2004US20040023471 Thermal production of nanowires
02/05/2004US20040023470 Novel material to improve image sensor yield during wafer sawing
02/05/2004US20040023468 Method for manufacturing a free-standing substrate made of monocrystalline semi-conductor material
02/05/2004US20040023467 Fabricating deeper and shallower trenches in semiconductor structures
02/05/2004US20040023466 Stacked wafer aligment method
02/05/2004US20040023465 Memory cell capacitors having an over/under configuration
02/05/2004US20040023464 Method for fabricating a deep trench capacitor for dynamic memory cells
02/05/2004US20040023463 Heterojunction bipolar transistor and method for fabricating the same
02/05/2004US20040023462 Gate dielectric and method
02/05/2004US20040023461 Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics
02/05/2004US20040023460 Double-gate fet with planarized surfaces and self-aligned silicides
02/05/2004US20040023459 Semiconductor device including gate insulation films having different thicknesses
02/05/2004US20040023458 Manufacturing method of flash memory
02/05/2004US20040023457 Global column select structure for accessing a memory
02/05/2004US20040023456 Method for fabricating capacitor in semiconductor device
02/05/2004US20040023455 Methods of forming memory cells, and memory cell arrays
02/05/2004US20040023454 Method for utilizing re-oxidation of nitride layer to form super thin nitride gate oxide layer
02/05/2004US20040023453 Supercritical fluid-assisted deposition of materials on semiconductor substrates
02/05/2004US20040023452 Method of passivating an oxide surface subjected to a conductive material anneal
02/05/2004US20040023451 Non-volatile memory device having floating trap type memory cell and method of forming the same
02/05/2004US20040023449 Self-aligned, planarized thin-film transistors, devices employing the same, and methods of fabrication thereof
02/05/2004US20040023448 Process for production of SOI substrate and process for production of semiconductor device
02/05/2004US20040023447 Organic thin film transistor and method of manufacturing the same, and semiconductor device having the organic thin film transistor
02/05/2004US20040023446 Method of manufacturing thin film transistor, method of manufacturing flat panel display, thin film transistor, and flat panel display
02/05/2004US20040023445 Electronic circuit
02/05/2004US20040023444 Method of manufacturing a semiconductor device
02/05/2004US20040023443 Methods for manufacturing SOI substrate using wafer bonding and complementary high voltage bipolar transistor using the SOI substrate
02/05/2004US20040023441 Edge intensive antifuse and method for making the same
02/05/2004US20040023440 Mosfet anti-fuse structure
02/05/2004US20040023439 Apparatus and method for manufacturing semiconductor device
02/05/2004US20040023438 Semiconductor package with a chip connected to a wiring substrate using bump electrodes and underfilled with sealing resin
02/05/2004US20040023437 Method for optical module packaging of flip chip bonding
02/05/2004US20040023436 Structure of high performance combo chip and processing method
02/05/2004US20040023433 High-density interconnection of temperature sensitive electronic devices
02/05/2004US20040023431 Method for fabricating n-type carbon nanotube device
02/05/2004US20040023430 Method for forming a micro-mechanical component in a semiconductor wafer, and a semiconductor wafer comprising a micro-mechanical component formed therein
02/05/2004US20040023428 Porous gas sensors and method of preparation thereof
02/05/2004US20040023427 Forming indium nitride (InN) and indium gallium nitride (InGaN) quantum dots grown by metal-organic-vapor-phase-epitaxy (MOCVD)
02/05/2004US20040023426 Method of fabricating a light emitting device, and light emitting device
02/05/2004US20040023425 Method of forming a color filter on a substrate having pixel driving elements
02/05/2004US20040023424 Etch stop control for MEMS device formation
02/05/2004US20040023423 Semiconductor layer formed by selective deposition and method for depositing semiconductor layer
02/05/2004US20040023420 Method for reduced photoresist usage
02/05/2004US20040023419 System and method for monitoring contamination
02/05/2004US20040023418 Flash assisted annealing
02/05/2004US20040023417 Ferroelectric capacitor having upper electrode lamination and manufacture thereof
02/05/2004US20040023416 Method for forming a paraelectric semiconductor device
02/05/2004US20040023403 Film evaluating method, temperature measuring method, and semiconductor device manufacturing method