Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
03/2005
03/15/2005US6867478 Semiconductor device having improved alignment of an electrode terminal on a semiconductor chip and a conductor coupled to the electrode terminal
03/15/2005US6867476 Vertical double diffused MOSFET and method of fabricating the same
03/15/2005US6867475 Semiconductor device with an inductive element
03/15/2005US6867474 Monolithic circuit inductance
03/15/2005US6867473 Plating a conductive material on a dielectric material
03/15/2005US6867472 Reduced hot carrier induced parasitic sidewall device activation in isolated buried channel devices by conductive buried channel depth optimization
03/15/2005US6867465 Method of designing semiconductor integrated circuit device and semiconductor integrated circuit device manufactured using the same
03/15/2005US6867463 Silicon nitride read-only-memory
03/15/2005US6867462 Semiconductor device using an SOI substrate and having a trench isolation and method for fabricating the same
03/15/2005US6867460 FinFET SRAM cell with chevron FinFET logic
03/15/2005US6867459 Isotopically pure silicon-on-insulator wafers and method of making same
03/15/2005US6867458 Semiconductor device and method for fabricating the same
03/15/2005US6867457 Semiconductor device and liquid jetting device using the same
03/15/2005US6867455 Semiconductor device with a metal insulator semiconductor transistor
03/15/2005US6867453 Memory device and fabrication method thereof
03/15/2005US6867452 Interlayer oxide containing thin films for high dielectric constant application of the formula AB2O6 or AB2O7
03/15/2005US6867451 Semiconductor device and method for manufacturing the same
03/15/2005US6867450 Semiconductor memory device with surface strap and method of fabricating the same
03/15/2005US6867449 Capacitor having RuSixOy-containing adhesion layers
03/15/2005US6867448 Electro-mechanically polished structure
03/15/2005US6867447 Ferroelectric memory cell and methods for fabricating the same
03/15/2005US6867446 Semiconductor memory device
03/15/2005US6867445 Semiconductor memory devices including different thickness dielectric layers for the cell transistors and refresh transistors thereof
03/15/2005US6867443 Parallel, individually addressable probes for nanolithography
03/15/2005US6867440 Self-aligned bipolar transistor without spacers and method for fabricating same
03/15/2005US6867439 Field-effect transistor using a group III-V compound semiconductor
03/15/2005US6867437 Semiconductor device
03/15/2005US6867434 Active matrix electro-luminescent display with an organic leveling layer
03/15/2005US6867433 Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors
03/15/2005US6867432 Semiconductor device having SiOxNy gate insulating film
03/15/2005US6867431 Semiconductor device and method for manufacturing the same
03/15/2005US6867430 Substrate identification circuit and semiconductor device
03/15/2005US6867428 Strained silicon NMOS having silicon source/drain extensions and method for its fabrication
03/15/2005US6867426 Light emitting diode having a transparent substrate
03/15/2005US6867425 Lateral phase change memory and method therefor
03/15/2005US6867424 Wafer defect inspection machine having a dual illumination system
03/15/2005US6867422 Apparatus for ion implantation
03/15/2005US6867325 Organosiloxane polymer, photo-curable resin composition, patterning process, and substrate-protecting coat
03/15/2005US6867153 Method of purging wafer receiving jig, wafer transfer device, and method of manufacturing semiconductor device
03/15/2005US6867152 Properties of a silica thin film produced by a rapid vapor deposition (RVD) process
03/15/2005US6867151 Mask for sequential lateral solidification and crystallization method using thereof
03/15/2005US6867150 Ozone treatment method and ozone treatment apparatus
03/15/2005US6867148 Adjustment concentration of ozone dissolved in acid solution; corrosion resistance
03/15/2005US6867147 Method of surface treatment of semiconductor
03/15/2005US6867146 Plasma processing method
03/15/2005US6867145 Method for fabricating semiconductor device using photoresist pattern formed with argon fluoride laser
03/15/2005US6867144 Apparatus and method for plasma processing high-speed semiconductor circuits with increased yield
03/15/2005US6867143 Method for etching a semiconductor substrate using germanium hard mask
03/15/2005US6867142 Method to prevent electrical shorts between tungsten interconnects
03/15/2005US6867141 Method for fabricating semiconductor device and forming interlayer dielectric film using high-density plasma
03/15/2005US6867140 Metal layer; mixture of liquid carrier, oxidizer and terminating compound
03/15/2005US6867139 Method of manufacturing semiconductor device
03/15/2005US6867138 Method of chemical/mechanical polishing of the surface of semiconductor device
03/15/2005US6867137 Fabrication method for a semiconductor structure having a partly filled trench
03/15/2005US6867136 Method for electrochemically processing a workpiece
03/15/2005US6867135 Via bottom copper/barrier interface improvement to resolve via electromigration and stress migration
03/15/2005US6867132 Large line conductive pads for interconnection of stackable circuitry
03/15/2005US6867131 Apparatus and method of increasing sram cell capacitance with metal fill
03/15/2005US6867130 Enhanced silicidation of polysilicon gate electrodes
03/15/2005US6867129 Method of improving the top plate electrode stress inducting voids for 1T-RAM process
03/15/2005US6867128 Method for making an electronic component with self-aligned drain and gate, in damascene architecture
03/15/2005US6867127 Diamond metal-filled patterns achieving low parasitic coupling capacitance
03/15/2005US6867126 Method to increase cracking threshold for low-k materials
03/15/2005US6867125 Creating air gap in multi-level metal interconnects using electron beam to remove sacrificial material
03/15/2005US6867124 Integrated circuit packaging design and method
03/15/2005US6867122 Redistribution process
03/15/2005US6867120 Method of fabricating a semiconductor device with a gold conductive layer and organic insulating layer
03/15/2005US6867119 Nitrogen oxidation to reduce encroachment
03/15/2005US6867118 Semiconductor memory and method for fabricating the same
03/15/2005US6867117 Organic device including semiconducting layer aligned according to microgrooves of photoresist layer
03/15/2005US6867116 Fabrication method of sub-resolution pitch for integrated circuits
03/15/2005US6867115 Compound semiconductor device
03/15/2005US6867113 In-situ deposition and doping process for polycrystalline silicon layers and the resulting device
03/15/2005US6867112 Method of fabricating nitride semiconductor device
03/15/2005US6867111 Method of manufacturing modules with an integrated circuit
03/15/2005US6867110 Separating apparatus and processing method for plate member
03/15/2005US6867108 Wiring line assembly and method for manufacturing the same, and thin film transistor array substrate having the wiring line assembly and method for manufacturing the same
03/15/2005US6867107 Variable capacitance device and process for manufacturing the same
03/15/2005US6867106 Semiconductor device and method for fabricating the same
03/15/2005US6867105 Bipolar transistor and method of fabricating a bipolar transistor
03/15/2005US6867104 Method to form a structure to decrease area capacitance within a buried insulator device
03/15/2005US6867103 Method of fabricating an ESD device on SOI
03/15/2005US6867102 Method for making a semiconductor device having a high-k gate dielectric
03/15/2005US6867101 Method of fabricating a semiconductor device having a nitride/high-k/nitride gate dielectric stack by atomic layer deposition (ALD) and a device thereby formed
03/15/2005US6867099 Spilt-gate flash memory structure and method of manufacture
03/15/2005US6867098 Method of forming nonvolatile memory device
03/15/2005US6867097 Method of making a memory cell with polished insulator layer
03/15/2005US6867096 Method of fabricating semiconductor device having capacitor
03/15/2005US6867095 Method for the fabrication of a semiconductor device utilizing simultaneous formation of contact plugs
03/15/2005US6867094 Method of fabricating a stacked capacitor for a semiconductor device
03/15/2005US6867093 Process for fabricating RuSixOy-containing adhesion layers
03/15/2005US6867092 Semiconductor integrated circuit device and the process of manufacturing the same for reducing the size of a memory cell by making the width of a bit line than a predetermined minimum size
03/15/2005US6867091 Method for forming deep trench capacitor with liquid phase deposition oxide as collar oxide
03/15/2005US6867090 Semiconductor device and method of manufacturing thereof
03/15/2005US6867089 Method of forming a bottle-shaped trench in a semiconductor substrate
03/15/2005US6867087 Formation of dual work function gate electrode
03/15/2005US6867086 Multi-step deposition and etch back gap fill process
03/15/2005US6867085 Insulated gate semiconductor device and method of manufacturing the same
03/15/2005US6867084 Gate structure and method of forming the gate dielectric with mini-spacer
03/15/2005US6867082 Nonvolatile memory cells having split gate structure and methods of fabricating the same
1 ... 3940 3941 3942 3943 3944 3945 3946 3947 3948 3949 3950 3951 3952 3953 3954 3955 3956 3957 3958 3959 3960 ... 6590