Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
06/2005
06/02/2005WO2005050699A2 Method of forming a semiconductor package and structure thereof
06/02/2005WO2005050697A2 Method for forming wavy nanostructures
06/02/2005WO2005050653A2 Stress assisted current driven switching for magnetic memory applications
06/02/2005WO2005050628A1 Method for fabricating giant magnetoresistive (gmr) devices
06/02/2005WO2005050597A1 Light-emitting device and method for manufacturing the same
06/02/2005WO2005050551A1 Electronic tag producing method
06/02/2005WO2005050324A2 A method and apparatus for producing microchips
06/02/2005WO2005050316A2 Method involving a mask or a reticle
06/02/2005WO2005050257A2 High temperature imaging device
06/02/2005WO2005050171A2 Methods and compositions relating to single reactive center reagents
06/02/2005WO2005049957A2 High temperature environment tool system and method
06/02/2005WO2005049887A2 Methods for the deposition of silver oxide films and patterned films
06/02/2005WO2005049884A2 Method for depositing silicon carbide and ceramic films
06/02/2005WO2005049287A1 Vacuum suction head, and vacuum suction device and table using the same
06/02/2005WO2005049269A2 Chemical mechanical planarization pad
06/02/2005WO2005049240A1 Exhaust gas treatment
06/02/2005WO2005038882A3 Electronic device and method of manufacturing thereof
06/02/2005WO2005036612A3 Ferroelectric capacitor with a complex-oxide hard-mask top electrode and method for manufacturing the same
06/02/2005WO2005036589A3 Position shift detection mark, wafer, and pattern position shift measurement method
06/02/2005WO2005034208A3 METHOD TO REDUCE STACKING FAULT NUCLEATION SITES AND REDUCE Vf DRIFT IN BIPOLAR DEVICES
06/02/2005WO2005033376A3 Plating method and apparatus
06/02/2005WO2005031811A3 Process and integration scheme for fabricating conductive components through-vias and semiconductor components including conductive through-wafer vias
06/02/2005WO2005029184A3 Positive photoresist composition and resist pattern formation
06/02/2005WO2005024932A3 Apparatus and method for removing semiconductor chip
06/02/2005WO2005022591A9 Reversible leadless package and methods of making and using same
06/02/2005WO2005020294A3 “control of etch and deposition processes”
06/02/2005WO2005017964A3 Structure and method of making strained semiconductor cmos transistors having lattice-mismatched source and drain regions
06/02/2005WO2005004221A3 Low-k-dielectric material
06/02/2005WO2005001908A3 Strained semiconductor device and method of manufacture
06/02/2005WO2004102635A3 Methods for preserving strained semiconductor layers during oxide layer formation
06/02/2005WO2004095603A3 Method of producing membrane electrode assemblies
06/02/2005WO2004082347A3 Solder on a sloped surface
06/02/2005WO2004070796A3 Tailoring nitrogen profile in silicon oxynitride using rapid thermal annealing with ammonia under ultra-low pressure
06/02/2005WO2004032191A3 Applications of nano-enabled large area macroelectronic substrates incorporating nanowires and nanowire composites
06/02/2005WO2004001800A3 Chip package sealing method
06/02/2005WO2003046950A3 Semiconductor component handling device having a performance film
06/02/2005US20050120328 Method and system for increasing product yield by controlling lithography on the basis of electrical speed data
06/02/2005US20050120325 Method of verifying corrected photomask-pattern results and device for the same
06/02/2005US20050120319 Timing closure methodology
06/02/2005US20050120318 Apparatus and method for designing semiconductor integrated circuit
06/02/2005US20050120315 Simulation model for designing semiconductor devices, apparatus for simulating the designing of semiconductor devices, method of simulating the designing of semiconductor devices, computer-readable recording medium storing a program for simulating the designing of semiconductor devices, semiconductor device, and method of manufacturing the semiconductor device
06/02/2005US20050120156 Semiconductor integrated circuit
06/02/2005US20050119852 Semiconductor test data analysis system
06/02/2005US20050119850 Testing system, a computer implemented testing method and a method for manufacturing electronic devices
06/02/2005US20050119844 Apparatus and method for inspecting patterns on wafers
06/02/2005US20050119843 Semiconductor production system
06/02/2005US20050119795 Anti-vibration technique
06/02/2005US20050119787 Transport system with multiple-load-port stockers
06/02/2005US20050119778 Coding method with dynamic positioning
06/02/2005US20050119420 Units of 9,9-bis(hydroxyphenyl)fluorene and heteroaromatic rings such as pyridine and thiophene moieties as low k dielectric material with good thermal stability, for forming a metal interconnect; traps copper or copper ions to prevent undesirable diffusion from conductive layer
06/02/2005US20050119360 Producing a porous material in which the density of the matrix of a primary material is increased during the production process without shrinkage; hard to shrink even after heat treatment
06/02/2005US20050119143 corrosion resistance; removing photoresist residues; using aqueous solution containing fluoride compound
06/02/2005US20050119142 Cleaning agent composition for a positive or a negative photoresist
06/02/2005US20050118938 Wafer processing machine
06/02/2005US20050118937 Polishing apparatus, polishing method, and semiconductor device fabrication method
06/02/2005US20050118936 Integrated pad and belt for chemical mechanical polishing
06/02/2005US20050118935 Substrate holding apparatus
06/02/2005US20050118933 Wafer polishing method
06/02/2005US20050118845 Anisotropically electroconductive adhesive film, method for the production thereof, and semiconductor devices
06/02/2005US20050118839 Chemical mechanical polish process control method using thermal imaging of polishing pad
06/02/2005US20050118838 Semiconductor device and method of manufacturing the same
06/02/2005US20050118837 Method to form ultra high quality silicon-containing compound layers
06/02/2005US20050118836 Dielectrics with improved leakage characteristics
06/02/2005US20050118835 Lithographic projection apparatus, mirror, method of supplying a protective cap layer, device manufacturing method and device manufactured accordingly
06/02/2005US20050118834 Film forming method
06/02/2005US20050118833 Method for manufacturing semiconductor device
06/02/2005US20050118832 Removal of MEMS sacrificial layers using supercritical fluid/chemical formulations
06/02/2005US20050118831 Gas assisted method for applying resist stripper and gas-resist stripper combinations
06/02/2005US20050118830 Method of processing a workpiece
06/02/2005US20050118829 Method for fabricating semiconductor device
06/02/2005US20050118828 Method for removing photoresist
06/02/2005US20050118827 Method for manufacturing a semiconductor device
06/02/2005US20050118826 Ultra-thin Si MOSFET device structure and method of manufacture
06/02/2005US20050118825 Process for producing group III nitride compound semiconductor
06/02/2005US20050118824 Multi-step chemical mechanical polishing of a gate area in a FinFET
06/02/2005US20050118823 Wafer processing method and wafer processing apparatus
06/02/2005US20050118822 Apparatus and process for bulk wet etch with leakage protection
06/02/2005US20050118821 Slurry for CMP, polishing method and method of manufacturing semiconductor device
06/02/2005US20050118820 CMP abrasive, liquid additive for CMP abrasive and method for polishing substrate
06/02/2005US20050118819 Post-CMP treating liquid and method for manufacturing semiconductor device
06/02/2005US20050118818 Etching method, method of manufacturing semiconductor device, and semiconductor device
06/02/2005US20050118817 Resist pattern forming method, magnetic recording medium manufacturing method and magnetic head manufacturing method
06/02/2005US20050118816 Method for fabricating a semiconductor component
06/02/2005US20050118815 Method of manufacturing optical semiconductor integrated circuit device
06/02/2005US20050118814 Method for depositing silicon nitride layer of semiconductor device
06/02/2005US20050118813 Removal of MEMS sacrificial layers using supercritical fluid/chemical formulations
06/02/2005US20050118812 Method of detecting, identifying and correcting process performance
06/02/2005US20050118811 Aluminum alloy film for wiring and sputter target material for forming the film
06/02/2005US20050118810 Method of cleaning surface of semiconductor substrate, method of manufacturing thin film, method of manufacturing semiconductor device, and semiconductor device
06/02/2005US20050118809 Manufacturing method of semiconductor device
06/02/2005US20050118808 Method of reducing the pattern effect in the CMP process
06/02/2005US20050118807 Ald deposition of ruthenium
06/02/2005US20050118806 Method for forming an electrical interconnection providing improved surface morphology of tungsten
06/02/2005US20050118805 Method of fabricating semiconductor integrated circuit device
06/02/2005US20050118804 Formation of boride barrier layers using chemisorption techniques
06/02/2005US20050118803 Building metal pillars in a chip for structure support
06/02/2005US20050118802 Method for implementing poly pre-doping in deep sub-micron process
06/02/2005US20050118801 Technique for forming a gate electrode by using a hard mask
06/02/2005US20050118800 Method of filling structures for forming via-first dual damascene interconnects
06/02/2005US20050118799 Method and structure for the adhesion between dielectric layers
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