Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
05/2005
05/31/2005US6900691 Semiconductor integrated circuit
05/31/2005US6900689 CMOS reference voltage circuit
05/31/2005US6900667 Logic constructions and electronic devices
05/31/2005US6900655 Determination of whether integrated circuit is acceptable or not in wafer-level burn-in test
05/31/2005US6900654 Method and apparatus for evaluating a known good die using both wire bond and flip-chip interconnects
05/31/2005US6900653 Needle fixture of a probe card in semiconductor inspection equipment and needle fixing method thereof
05/31/2005US6900652 Flexible membrane probe and method of use thereof
05/31/2005US6900646 Probing device and manufacturing method thereof, as well as testing apparatus and manufacturing method of semiconductor with use thereof
05/31/2005US6900645 Semiconductor device test method and semiconductor device tester
05/31/2005US6900632 Spin exciting method and magnetic resonance imaging system
05/31/2005US6900628 Semiconductor integrated circuit allowing proper detection of pin contact failure
05/31/2005US6900627 Apparatus and method for testing semiconductor integrated circuit
05/31/2005US6900551 Semiconductor device with alternate bonding wire arrangement
05/31/2005US6900550 Semiconductor device including adhesive agent layer with embedded conductor bodies
05/31/2005US6900548 Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument
05/31/2005US6900546 Semiconductor memory device and method for manufacturing the same
05/31/2005US6900542 Semiconductor device having increased adhesion between a barrier layer for preventing copper diffusion and a conductive layer, and method of manufacturing the same
05/31/2005US6900539 Having via holes/metals improved in terms of reliability therein for connecting upper and lower interconnect layers to each other
05/31/2005US6900538 Integrating chip scale packaging metallization into integrated circuit die structures
05/31/2005US6900536 Method for producing an electrical circuit
05/31/2005US6900534 Direct attach chip scale package
05/31/2005US6900522 Chamfered semiconductor wafer and method of manufacturing the same
05/31/2005US6900521 Vertical transistors and output prediction logic circuits containing same
05/31/2005US6900520 Semiconductor element and manufacturing method thereof
05/31/2005US6900519 Diffused extrinsic base and method for fabrication
05/31/2005US6900518 Semiconductor device
05/31/2005US6900515 Use of DAR coating to modulate the efficiency of laser fuse blows
05/31/2005US6900514 Semiconductor device having a capacitance device
05/31/2005US6900513 Semiconductor memory device and manufacturing method thereof
05/31/2005US6900509 Optical receiver package
05/31/2005US6900506 Method and structure for a high voltage junction field effect transistor
05/31/2005US6900504 Integrated structure effective to form a MOS component in a dielectrically insulated well
05/31/2005US6900503 SRAM formed on SOI substrate
05/31/2005US6900502 Strained channel on insulator device
05/31/2005US6900501 Silicon on insulator device with improved heat removal
05/31/2005US6900500 Buried transistors for silicon on insulator technology
05/31/2005US6900499 Non-volatile memory and semiconductor device
05/31/2005US6900498 Barrier structures for integration of high K oxides with Cu and Al electrodes
05/31/2005US6900497 Integrated circuit with a capacitor comprising an electrode
05/31/2005US6900496 Capacitor constructions
05/31/2005US6900495 Layer arrangement, memory cell, memory cell arrangement and method for producing a layer arrangement
05/31/2005US6900494 Method of using high-k dielectric materials to reduce soft errors in SRAM memory cells, and a device comprising same
05/31/2005US6900492 Integrated circuit device with P-type gate memory cell having pedestal contact plug and peripheral circuit
05/31/2005US6900490 Magnetic random access memory
05/31/2005US6900487 Wiring layer structure for ferroelectric capacitor
05/31/2005US6900486 Hollow with dielectric films; electrodes; spin coating ; controlled etching
05/31/2005US6900483 Semiconductor device and method for manufacturing the same
05/31/2005US6900482 Semiconductor device having divided active regions with comb-teeth electrodes thereon
05/31/2005US6900481 Non-silicon semiconductor and high-k gate dielectric metal oxide semiconductor field effect transistors
05/31/2005US6900479 Stochastic assembly of sublithographic nanoscale interfaces
05/31/2005US6900478 Multi-threshold MIS integrated circuit device and circuit design method thereof
05/31/2005US6900464 Thin film transistor device and method of manufacturing the same, and liquid crystal display device
05/31/2005US6900463 Semiconductor device
05/31/2005US6900462 Semiconductor device and manufacturing method thereof
05/31/2005US6900461 Overcoating substrate with barrier electrodes; then dielectrics; silver, molybdenum alloy
05/31/2005US6900460 Semiconductor device and method of manufacturing the same
05/31/2005US6900459 Apparatus for automatically positioning electronic dice within component packages
05/31/2005US6900455 Multilayer dielectric tunnel barrier used in magnetic tunnel junction devices, and its method of fabrication
05/31/2005US6900443 Charged particle beam device for inspecting or structuring a specimen
05/31/2005US6900434 Method and device for separating ion mass, and ion doping device
05/31/2005US6900413 Hot wall rapid thermal processor
05/31/2005US6900284 Poly-o-hydroxyamides, polybenzoxazoles, processes for producing poly-o-hydroxyamides, processes for producing polybenzoxazoles, dielectrics including a polybenzoxazole, electronic components including the dielectrics, and processes for manufacturing the electronic components
05/31/2005US6900149 Carbon-containing aluminum nitride sintered compact and ceramic substrate for use in equipment for manufacturing or inspecting semiconductor
05/31/2005US6900144 Film-forming surface reforming method and semiconductor device manufacturing method
05/31/2005US6900143 Strained silicon MOSFETs having improved thermal dissipation
05/31/2005US6900142 Inhibition of tin oxide formation in lead free interconnect formation
05/31/2005US6900141 Method of forming a resist pattern and fabricating tapered features
05/31/2005US6900140 Anisotropic etching of organic-containing insulating layers
05/31/2005US6900139 Method for photoresist trim endpoint detection
05/31/2005US6900138 Oxygen plasma treatment for nitride surface to reduce photo footing
05/31/2005US6900137 Dry etch process to edit copper lines
05/31/2005US6900136 Method for reducing reactive ion etching (RIE) lag in semiconductor fabrication processes
05/31/2005US6900135 Buffer station for wafer backside cleaning and inspection
05/31/2005US6900134 Method for forming openings in a substrate using bottom antireflective coatings
05/31/2005US6900133 Method of etching variable depth features in a crystalline substrate
05/31/2005US6900132 Single workpiece processing system
05/31/2005US6900131 Method of manufacturing semiconductor device
05/31/2005US6900130 Method for locally heating a region in a semiconductor substrate
05/31/2005US6900129 CVD of tantalum and tantalum nitride films from tantalum halide precursors
05/31/2005US6900128 Activation of oxides for electroless plating
05/31/2005US6900127 Multilayer integrated circuit copper plateable barriers
05/31/2005US6900126 Method of forming metallized pattern
05/31/2005US6900125 Method of manufacturing a semiconductor device including a multi-layer interconnect structure
05/31/2005US6900124 Patterning for elliptical Vss contact on flash memory
05/31/2005US6900123 BARC etch comprising a selective etch chemistry and a high polymerizing gas for CD control
05/31/2005US6900122 Low-temperature grown high-quality ultra-thin praseodymium gate dielectrics
05/31/2005US6900121 Laser thermal annealing to eliminate oxide voiding
05/31/2005US6900120 Liquid crystal display device and method for manufacturing the same
05/31/2005US6900119 Agglomeration control using early transition metal alloys
05/31/2005US6900118 Method for preventing contact defects in interlayer dielectric layer
05/31/2005US6900117 Method of fabricating bumps utilizing a resist layer having photosensitive agent and resin
05/31/2005US6900116 High permeability thin films and patterned thin films to reduce noise in high speed interconnections
05/31/2005US6900115 Deposition over mixed substrates
05/31/2005US6900114 Separating apparatus, separating method, and method of manufacturing semiconductor substrate
05/31/2005US6900113 Method for producing bonded wafer and bonded wafer
05/31/2005US6900112 Process for forming shallow trench isolation region with corner protection layer
05/31/2005US6900111 Method of forming a thin oxide layer having improved reliability on a semiconductor surface
05/31/2005US6900110 Chip scale package with compliant leads
05/31/2005US6900109 Method of manufacturing a semiconductor device with a vertical drain drift layer of the alternating-conductivity-type
05/31/2005US6900107 Devices containing platinum-iridium films and methods of preparing such films and devices
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