Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
10/2005
10/27/2005WO2005064662A3 A semiconductor substrate with solid phase epitaxial regrowth with reduced depth of doping profile and method of producing same
10/27/2005WO2005060000A3 Bridge field-effect transistor storage cell, device comprising said cells and method for producing a bridge field-effect transistor storage cell
10/27/2005WO2005059993A3 Packaging substrates for integrated circuits and soldering methods
10/27/2005WO2005059961A3 Low crosstalk substrate for mixed-signal integrated circuits
10/27/2005WO2005050653A3 Stress assisted current driven switching for magnetic memory applications
10/27/2005WO2005048320A3 Method for integrating metals having different work functions to form cmos gates having a high-k gate dielectric and related structure
10/27/2005WO2005034203A3 Method and apparatus for a dual substrate package
10/27/2005WO2005033801A3 Adaptive thermal control of lithographic chemical processes
10/27/2005WO2005029549A3 Method and system for facilitating bi-directional growth
10/27/2005WO2005008730A3 Low cost, high performance flip chip package structure
10/27/2005WO2004095531A3 Method and system for temperature control of a substrate
10/27/2005WO2004092566B1 Metal seal packaging for organic light emitting diode device
10/27/2005WO2004068550A3 Interconnect structures incorporating low-k dielectric barrier films
10/27/2005WO2004024983A3 Method and apparatus for electroless deposition with temperature-controlled chuck
10/27/2005WO2001086353A9 Polymers containing oxygen and sulfur alicyclic units and photoresist compositions comprising same
10/27/2005US20050240890 Circuit layout and semiconductor substrate for photosensitive chip
10/27/2005US20050240850 Multicore processor test method
10/27/2005US20050239984 Copolymers derived from fluorinated olefin, polycyclic ethylenically unsaturated polycyclic monomer with a fused 4-membered ring, useful for photoimaging, coated substrates, for imaging in the production of semiconductor devices, plasma etch resistance and adhesive properties
10/27/2005US20050239953 Radiation curable composition, storing method thereof, forming method of cured film, patterning method, use of pattern, electronic components and optical waveguide
10/27/2005US20050239932 Composition for antireflection coating and method for forming pattern
10/27/2005US20050239673 Containing hydrogen peroxide, sulfolane, optionally tetramethylammonium hydroxide, and either trans-1,2-cyclohexanediamine tetraacetic acid or ethylenediaminetetrakis(methylene phosphonic acid); cleans copper residues, SiO2,and low- and high- kappa dielectrics
10/27/2005US20050239672 Non-ionic surfactant, an alkaline compound and pure water; reduces damage to silicon germanium, removes impurities and improves rough surfaces
10/27/2005US20050239431 Transmission circuit, CMOS semiconductor device, and design method thereof
10/27/2005US20050239382 Planarizing solutions including abrasive elements, and methods for manufacturing and using such planarizing solutions
10/27/2005US20050239372 Substrate polishing apparatus
10/27/2005US20050239371 Pressure control system and polishing apparatus
10/27/2005US20050239299 Method for manufacturing a display device including irradiating overlapping regions
10/27/2005US20050239297 Growth of high-k dielectrics by atomic layer deposition
10/27/2005US20050239296 Top ARC polymers, method of preparation thereof and top ARC compositions comprising the same
10/27/2005US20050239295 Chemical treatment of material surfaces
10/27/2005US20050239294 Apparatus for depositing a multilayer coating on discrete sheets
10/27/2005US20050239293 Post treatment of low k dielectric films
10/27/2005US20050239292 Device for etching semicnductors with a large surface area
10/27/2005US20050239291 Nonlithographic method of defining geometries for plasma and/or ion implantation treatments on a semiconductor wafer
10/27/2005US20050239290 Trench photolithography rework for removal of photoresist residue
10/27/2005US20050239289 Method for reducing integrated circuit defects
10/27/2005US20050239288 Sequential reducing plasma and inert plasma pre-treatment method for oxidizable conductor layer
10/27/2005US20050239287 Silicide formation using a metal-organic chemical vapor deposited capping layer
10/27/2005US20050239286 Two-step stripping method for removing via photoresist during the fabrication of partial-via dual damascene features
10/27/2005US20050239285 Damascene process capable of avoiding via resist poisoning
10/27/2005US20050239284 Wiring structure for integrated circuit with reduced intralevel capacitance
10/27/2005US20050239283 Polishing method, polishing apparatus, and method of manufacturing semiconductor device
10/27/2005US20050239282 Method for forming self-aligned contact in semiconductor device
10/27/2005US20050239281 Photosensitive dielectric layer
10/27/2005US20050239280 Method of manufacturing semiconductor device
10/27/2005US20050239279 Integrated circuits including spacers that extend beneath a conductive line and methods of fabricating the same
10/27/2005US20050239278 Process of forming a composite diffusion barrier in copper/organic low-k damascene technology
10/27/2005US20050239277 Interconnect and a method of manufacture therefor
10/27/2005US20050239276 Bump forming method and system using bump material including liquid
10/27/2005US20050239275 Compliant multi-composition interconnects
10/27/2005US20050239274 Method for growth of group III-V semiconductor material on a dielectric
10/27/2005US20050239273 Protective metal structure and method to protect low -K dielectric layer during fuse blow process
10/27/2005US20050239272 Process for producing a multilayer arrangement having a metal layer
10/27/2005US20050239271 Heteroepitaxial growth method for gallium nitride
10/27/2005US20050239270 Method for producing a semiconductor element
10/27/2005US20050239269 Method for releasing stress of embedded chip and chip embedded structure
10/27/2005US20050239268 Integrated circuit with removable scribe street trim and test pads
10/27/2005US20050239267 Substrate manufacturing method
10/27/2005US20050239266 Method of forming trench isolation regions
10/27/2005US20050239265 Method of forming trench isolation regions
10/27/2005US20050239264 Materials suitable for shallow trench isolation
10/27/2005US20050239263 Diffusion-enhanced crystallization of amorphous materials to improve surface roughness
10/27/2005US20050239262 PCMO thin film with memory resistance properties
10/27/2005US20050239260 Compensated linearity voltage-control-capacitor device by standard CMOS process
10/27/2005US20050239259 High voltage power device with low diffusion pipe resistance
10/27/2005US20050239258 Method of fabricating semiconductor device
10/27/2005US20050239257 Method of manufacturing a semiconductor integrated circuit device and a semiconductor integrated circuit device
10/27/2005US20050239256 Shallow low energy ion implantation into pad oxide for improving threshold voltage stability
10/27/2005US20050239255 Formation of lattice-tuning semiconductor substrates
10/27/2005US20050239254 Quasi-plannar and FinFET-like transistors on bulk silicon
10/27/2005US20050239253 Integrated circuit structure with improved LDMOS design
10/27/2005US20050239252 Methods of forming integrated circuit devices having field effect transistors of different types in different device regions
10/27/2005US20050239251 Semiconductor device and method for fabricating the same
10/27/2005US20050239250 Ultra dense non-volatile memory array
10/27/2005US20050239249 Vertical floating gate transistor
10/27/2005US20050239248 Method for manufacturing nonvolatile memory device
10/27/2005US20050239247 Novel architecture to monitor isolation integrity between floating gate and source line
10/27/2005US20050239246 Method and apparatus for fabricating a memory device with a dielectric etch stop layer
10/27/2005US20050239245 Nonvolatile semiconductor memory and method of operating the same
10/27/2005US20050239244 Methods of forming storage nodes for a DRAM array
10/27/2005US20050239243 Methods of forming DRAM arrays
10/27/2005US20050239242 structure and method of manufacturing a finFet device having stacked fins
10/27/2005US20050239241 High speed lateral heterojunction MISFETS realized by 2-dimensional bandgap engineering and methods thereof
10/27/2005US20050239240 Process for fabricating semiconductor device
10/27/2005US20050239239 Thin-film transistor and method of fabricating the same
10/27/2005US20050239237 Method for producing a BGA chip module and BGA chip module
10/27/2005US20050239235 Method for manufacturing an adhesive substrate with a die-cavity sidewall
10/27/2005US20050239233 Recording head unit and method of producing the same
10/27/2005US20050239231 Method for making a microelectromechanical system using a flexure protection layer
10/27/2005US20050239229 Method of connecting wiring member
10/27/2005US20050239227 Light emitting diode component
10/27/2005US20050239226 Method for manufacturing organic electroluminescence device and electronic apparatus
10/27/2005US20050239224 Method and apparatus for measuring relative dielectric constant
10/27/2005US20050239223 Method and device for monitoring the etching operation for a regular depth structure in a semiconductor substrate
10/27/2005US20050239222 Run-to-run control of backside pressure for CMP radial uniformity optimization based on center-to-edge model
10/27/2005US20050239221 Method for conductive film quality evaluation
10/27/2005US20050239220 Rate gyroscope and accelerometer multisensor, and method of fabricating same
10/27/2005US20050239219 Process for fabrication of a ferrocapacitor with a large effective area
10/27/2005US20050239218 Ferroelectric capacitor having a substantially planar dielectric layer and a method of manufacture therefor
10/27/2005US20050239002 Semiconductor multilevel interconnect structure
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