Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
12/2005
12/15/2005DE4412915B4 Plasmabehandlungsanlage, Verfahren zu deren Betrieb und Verwendung derselben Plasma treatment equipment, process for their operation and use of the same
12/15/2005DE4207226B4 Integrierte Schaltung Integrated circuit
12/15/2005DE3811372B4 Vorrichtung zum Einschleusen eines Gegenstands in eine Reaktionskammer Means for introducing an object into a reaction chamber
12/15/2005DE19953322B4 Handhabungselement für Kleinteile und Verfahren zur Herstellung Handling member for small items and methods for preparing
12/15/2005DE19907621B4 Ätzmaskierung Etching mask
12/15/2005DE19859090B4 Verfahren zum Herstellen von Gateoxiden mit verschiedenen Dicken A process for the manufacture of gate oxides having different thicknesses
12/15/2005DE19859023B4 Verfahren und Vorrichtung zur Trennung von Schichten und Bauteilen Method and apparatus for separation of layers and components
12/15/2005DE19857356B4 Heteroübergangs-Bipolartransistor A heterojunction bipolar transistor
12/15/2005DE19747164B4 Anordnung zur Bearbeitung einer Substratscheibe Arrangement for processing a substrate wafer
12/15/2005DE19600049B4 Selbstbootstrapvorrichtung Selbstbootstrapvorrichtung
12/15/2005DE102005024199A1 Wafer grinding method for manufacture of integrated circuit, involves interposing shock absorbing material between wheel mounting and wheel base of grinding stone
12/15/2005DE102005024086A1 Verfahren zum Antrieb eines Galvanoscanners A method of driving a Galvanoscanners
12/15/2005DE102005022575A1 Non-volatile semiconductor memory e.g. flash memory, has floating gate whose two side surfaces are wave-shaped along lengthwise of channel region formed between source and floating junction regions
12/15/2005DE102005022306A1 Manufacture of semiconductor device comprises providing semiconductor substrate, forming mask layer over cell area and peripheral circuit area of substrate, and forming gates
12/15/2005DE102005021249A1 Halbleitervorrichtung Semiconductor device
12/15/2005DE102005015829A1 Verfahren zum Reinigen des Inneren einer Fern-Plasmaerzeugungsröhre sowie Vorrichtung und Verfahren zum Verarbeiten eines Substrats unter Verwendung derselben A method for cleaning the interior of a remote plasma generating tube as well as apparatus and method for processing a substrate using the same
12/15/2005DE102005014740A1 Bandexpansionsvorrichtung Band expander
12/15/2005DE102005013885A1 Halbleitervorrichtung und Herstellungsverfahren dafür A semiconductor device and manufacturing method thereof
12/15/2005DE102005005327A1 Feldefekttansistor, Transistoranordnung sowie Verfahren zur Herstellung eines halbleitenden einkristallinen Substrats und einer Transistoranordnung Feldefekttansistor, transistor arrangement and method of manufacturing a semiconductive single crystalline substrate and a transistor arrangement
12/15/2005DE102005004401A1 Korrosionshemmende Reinigungszusammensetzungen für Metallschichten und Muster an Halbleitersubstraten The corrosion inhibiting compositions for cleaning metal layers and patterns on semiconductor substrates
12/15/2005DE102005004110A1 Korrosionshemmende Reinigungszusammensetzungen für Metallschichten und Muster an Halbleitersubstraten The corrosion inhibiting compositions for cleaning metal layers and patterns on semiconductor substrates
12/15/2005DE102004063299A1 Halbleiterwaferprüfgerät und Sondenübertragungseinrichtung Halbleiterwaferprüfgerät and probe transmission device
12/15/2005DE102004063139A1 Verfahren zur Herstellung einer Split-Gate-Flash-Speichereinrichtung A process for producing a split-gate flash memory device
12/15/2005DE102004061575A1 Semiconductor device for electric power module, has metal layer connected to bonding wire, which is provided at front surface of substrate, so that metal layer overlaps capacitor
12/15/2005DE102004033645A1 Herstellungswerkzeug für eine Waferebene-Packung und Verfahren zum Anordnen von Chips Production tool for a wafer level package and method for disposing of chips
12/15/2005DE102004025279A1 Träger mit Lotkugelelementen und ein Verfahren zum Bestücken von Substraten mit Kugelkontakten Carrier with solder ball elements and a method for loading substrates with ball contacts
12/15/2005DE102004025150A1 Lagebestimmung eines Halbleitersubstrats auf einer Rotationsvorrichtung Orientation of a semiconductor substrate on a rotator
12/15/2005DE102004024886A1 Method for applying photoactive multilayer coatings to substrates comprises applying nitrogen-free, non-stoichiometric silicon oxide dielectric anti-reflection layer to substrate with surface to which photoactive resist can be applied
12/15/2005DE102004024665A1 Verfahren zum Herstellen von dielektrischen Mischschichten und kapazitives Element und Verwendung derselben The method for producing dielectric layers and mixing capacitive element and using the same
12/15/2005DE102004024661A1 Trench transistor manufacturing method, by back-forming layer in upper trench region, and semiconductor material on side walls of trench before forming new semiconductor material on side walls
12/15/2005DE102004024660A1 Integrated semiconductor device, has active trenches and spacing of directly adjacent contact trenches larger than half width of contact trenches
12/15/2005DE102004024659A1 Halbleiterbauteil Semiconductor device
12/15/2005DE102004024207A1 Verfahren und Vorrichtung zur Niedertemperaturepitaxie auf einer Vielzahl von Halbleitersubstraten Method and apparatus for Niedertemperaturepitaxie on a plurality of semiconductor substrates
12/15/2005DE102004023897A1 Manufacture of protected circuit tracks and contact pads on electronic device having diffusion barrier and copper seed layer, by making second negative-resist mask so that copper core and edge region are kept free
12/15/2005DE102004023752A1 Avoiding thickness reduction of redistribution layer in seed-layer etching, by applying sacrificial layer to protect copper layer below, lifting off mask and removing seed layer by etching
12/15/2005DE102004023739A1 Messgerät und Verfahren zum Betreiben eines Messgeräts zur optischen Inspektion eines Objekts Meter and method for operating a measuring device for optical inspection of an object
12/15/2005DE102004023462A1 Halbleiterchip mit Metallisierungsebenen und Verfahren zur Ausbildung von Leiterbahnstrukturen Semiconductor chip metallization and method for forming interconnect structures
12/15/2005DE102004023405A1 Dicing ultra-thin wafer in to multiple integrated circuits, by fixing carrier wafer to front of product wafer, forming separating trenches between integrated circuits
12/15/2005DE102004023301A1 Bridge field effect transistor memory cell has charge storage layer designed for selective charge carrier introduction or removal by application of given electrical potential
12/15/2005DE102004023193A1 Transistoranordnung und Herstellungsverfahren derselben Transistor device and manufacturing method thereof
12/15/2005DE102004022618A1 Manufacture of memory cell, selectively removing nano-porous mask layer to leave nano-point-like memory regions, and applying insulating layer so that memory regions are insulated from each other
12/15/2005DE102004022602A1 Verfahren zur Herstellung eines Grabenkondensators, Verfahren zur Herstellung einer Speicherzelle, Grabenkondensator und Speicherzelle A process for the preparation of a grave capacitor, A method for fabricating a memory cell, capacitor and memory cell grave
12/15/2005DE102004022402A1 Dry etching of layer sequence, for anisotropic etching of aluminum-containing substrates, by etching fourth layer in plasma comprising halogen-containing gas, and third layer in plasma comprising halogen- and nitrogen-containing gases
12/15/2005DE102004021790B3 Chemical analysis system for surface of ultra-thin layer of semiconductor wafer uses Photo Emission Electron Microscopy sensor in chamber with vacuum-tight window in front of photodetector
12/15/2005DE102004001108B4 Permanenter oder temporärer Schutz von Bauelementen mittels Schrumpffolie Permanent or temporary protection of components by shrink film
12/15/2005DE10161043B4 Chipanordnung Chip system
12/15/2005DE10085054B4 Trench-IGBT Trench IGBT
12/15/2005CA2567066A1 Methods of fabricating nitride-based transistors having regrown ohmic contact regions and nitride-based transistors having regrown ohmic contact regions
12/15/2005CA2564220A1 Systems and methods for nanowire growth and harvesting
12/14/2005EP1605738A1 Method for production of semiconductor package
12/14/2005EP1605736A2 Integrated circuits with copper metallization for interconnection
12/14/2005EP1605686A1 Solid state image sensor
12/14/2005EP1605560A2 Lightemitting semiconductor device and method for temperature stabilisation
12/14/2005EP1605522A1 Semiconductor light-emitting element and method for manufacturing same; integrated semiconductor light-emitting device and method for manufacturing same; image display and method for manufacturing same; and illuminating device and method for manufacturing same
12/14/2005EP1605521A2 Manufacturing method for a base piece made to adhere to an adhesive sheet, for a semiconductor wafer and for a semiconductor device
12/14/2005EP1605519A2 Semiconductor device and manufacturing method of the same
12/14/2005EP1605518A2 Zener diode and method for fabricating the same
12/14/2005EP1605517A2 Insulating barrier
12/14/2005EP1605510A1 Soi wafer and method for manufacturing same
12/14/2005EP1605509A1 Semiconductor device, process for producing the same and imaging device
12/14/2005EP1605506A2 Semiconductor device
12/14/2005EP1605505A1 Method for manufacturing a material compound wafer
12/14/2005EP1605504A1 Method for manufacturing a SOI wafer
12/14/2005EP1605503A2 Transfer method for the manufacturing of electronic devices
12/14/2005EP1605502A1 Transfer method for the manufacturing of electronic devices
12/14/2005EP1605501A1 Asymmetric channel doped MOS structure and method
12/14/2005EP1605500A1 Semiconductor device and method for manufacturing semiconductor device
12/14/2005EP1605499A2 Method for manufacturing a crystalline silicon layer
12/14/2005EP1605498A1 A method of manufacturing a semiconductor wafer
12/14/2005EP1605497A2 Capacitor and method for manufacturing the same
12/14/2005EP1605496A2 Substrate storage container
12/14/2005EP1605378A1 Method for generating hardware information
12/14/2005EP1605313A2 Lithographic apparatus and device manufacturing method
12/14/2005EP1605312A1 Radiation system, lithographic apparatus and device manufacturing method
12/14/2005EP1605310A2 Exposure system and pattern formation method
12/14/2005EP1605308A2 Apparatus
12/14/2005EP1605295A1 Optical modulator module
12/14/2005EP1605076A2 Method for preventing contamination during the fabrication of a semiconductor device
12/14/2005EP1604406A1 Transistor for active matrix display and a method for producing said transistor
12/14/2005EP1604405A1 A method for making a semiconductor device having a high-k gate dielectric
12/14/2005EP1604404A1 Semiconductor structure comprising a highly doped conductive channel region and method for producing a semiconductor structure
12/14/2005EP1604403A2 Angled implant for trench isolation
12/14/2005EP1604398A2 Magnetic memory cell junction and method for forming a magnetic memory cell junction
12/14/2005EP1604397A2 Shallow trench isolation in processes with strained silicon
12/14/2005EP1604396A2 Two-step post nitridation annealing for lower eot plasma nitrided gate dielectrics
12/14/2005EP1604395A2 Epitaxial semiconductor deposition methods and structures
12/14/2005EP1604394A2 Method of improving interlayer adhesion
12/14/2005EP1604393A2 System, method and apparatus for improved global dual-damascene planarization
12/14/2005EP1604392A1 Semiconductor mos, cmos devices and capacitors and method of manufacturing the same
12/14/2005EP1604391A1 Method of producing high quality relaxed silicon germanium layers
12/14/2005EP1604390A1 Method for the production of stress-relaxed layer structure on a non-lattice adapted substrate and utilization of said layer system in electronic and/or optoelectronic components
12/14/2005EP1604389A2 Processing system and method for thermally treating a substrate
12/14/2005EP1604388A2 Processing system and method for chemically treating a substrate
12/14/2005EP1604387A2 Processing system and method for treating a substrate
12/14/2005EP1604386A2 Method and apparatus for thermally insulating adjacent temperature controlled processing chambers
12/14/2005EP1604384A1 Installation for processing a substrate
12/14/2005EP1604247A2 A method of patterning photoresist on a wafer using an attenuated phase shift mask
12/14/2005EP1603702A2 Room temperature metal direct bonding
12/14/2005EP1603612A2 Protective sheath for a cannula
12/14/2005EP1590505A4 Composition and method for copper chemical mechanical planarization
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