Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
04/2006
04/06/2006WO2006035591A1 Method for forming copper wiring
04/06/2006WO2006035541A1 Semiconductor device
04/06/2006WO2006035411A2 Reduction of sheet resistance of phosphorus implanted poly-silicon
04/06/2006WO2006035387A1 Deep trench electrically isolated medium voltage cmos devices and method for making the same
04/06/2006WO2006035377A2 Integrated sicr metal thin film resistors for sige rf-bicmos technology
04/06/2006WO2006035281A1 Precursor for film formation and method for forming ruthenium-containing film
04/06/2006WO2006035134A1 Composite material for producing high-thermally conductive ribs for heat exchangers
04/06/2006WO2006035031A1 New structure for microelectronics and microsystem and manufacturing process
04/06/2006WO2006035017A1 Electronic device with a multi-layered ceramic substrate and a heat-removal body
04/06/2006WO2006034970A1 Semiconductor assembly comprising a tunnel contact and method for producing said assembly
04/06/2006WO2006034854A2 Semiconductor memory device having charge-trapping memory cells
04/06/2006WO2006034767A1 Electrical assembly and method for the production of an electrical assembly
04/06/2006WO2006034680A1 Semiconductor chip comprising a metal coating structure and associated production method
04/06/2006WO2006034679A2 Method for producing a strained layer on a substrate and layered structure
04/06/2006WO2006034672A2 Method for treating semiconductor substrates that are annealed by means of intensive light pulses
04/06/2006WO2006034664A1 Conductor frame for an electronic component and method for the production thereof
04/06/2006WO2006019670A3 Vibratable die attachment tool
04/06/2006WO2006014249A3 Use of a chalcogen plasma to form chalcogenide switching materials for nanoscale electronic devices
04/06/2006WO2006013508A3 Wafer with improved conductive loops in the dicing lines
04/06/2006WO2006013137A3 Method for etching a layer on a substrate
04/06/2006WO2006009444A3 Method and apparatus for inspecting a specimen surface and use of fluorescent materials
04/06/2006WO2006002138A3 Etch and deposition control for plasma implantation
04/06/2006WO2006001915A3 Semiconductor device with multiple semiconductor layers
04/06/2006WO2005124849A3 System and method for forming multi-component dielectric films
04/06/2006WO2005123988B1 Method of barrier layer surface treatment to enable direct copper plating on barrier metal
04/06/2006WO2005117121A3 Memory arrays; methods of forming memory arrays; and methods of forming contacts to bitlines
04/06/2006WO2005104147A3 Cmos-compatible light emitting aperiodic photonic structures
04/06/2006WO2005098977A3 Reflector packages and methods for packaging of a semiconductor light emitting device
04/06/2006WO2005079293A3 Integrated iii-nitride power devices
04/06/2006WO2005067657A3 Method of packaging an optical sensor
04/06/2006WO2005065436A3 Method and apparatus for maintaining parallelism of layers and/or achieving desired thicknesses of layers during the electrochemical fabrication of structures
04/06/2006WO2005065385A3 Power semiconductor devices and methods of manufacture
04/06/2006WO2005062998A8 Metal interconnect system and method for direct die attachment
04/06/2006WO2005003668A3 Microchannel heat exchangers and methods of manufacturing the same
04/06/2006WO2005001519A3 Embedded waveguide detectors
04/06/2006WO2004083901A3 Detection of macro-defects using micro-inspection inputs
04/06/2006WO2004027110A3 Additives to prevent degradation of alkyl-hydrogen siloxanes
04/06/2006US20060074510 Network-based photomask data entry interface and instruction generator for manufacturing photomasks
04/06/2006US20060074507 Information providing method and system
04/06/2006US20060074150 molding materials; fluidity; semiconductor chip arranged on a thin, multi-pin, long wire, narrow-pad-pitch, or a mounted substrate; free of molding defects, wire sweep, voids;
04/06/2006US20060073998 Supercritical carbon dioxide/chemical formulation for ashed and unashed aluminum post-etch residue removal
04/06/2006US20060073769 Polishing method
04/06/2006US20060073731 Multiple function wall cover plate
04/06/2006US20060073708 Strained silicon on insulator from film transfer and relaxation by hydrogen implantation
04/06/2006US20060073707 Low 1c screw dislocation 3 inch silicon carbide wafer
04/06/2006US20060073706 Etching silicon nitride from conductive oxide material (In2O3, RuO2) by adding an oxidant CO, NO, NO2, CO2) to chlorine or fluorine etching gas to improve selectivity resulting in silicon nitride spacers on the step structure suited for ferroelectric random access memory memory transistor fabrication
04/06/2006US20060073705 Method for dividing semiconductor wafer along streets
04/06/2006US20060073704 Method of forming bump that may reduce possibility of losing contact pad material
04/06/2006US20060073703 Dynamic edge bead removal
04/06/2006US20060073702 Memory structure and manufacturing as well as programming method thereof
04/06/2006US20060073701 Method of manufacturing a substrate with through electrodes
04/06/2006US20060073700 Method for forming a barrier layer in an integrated circuit in a plasma with source and bias power frequencies applied through the workpiece
04/06/2006US20060073699 Method for fabricating semiconductor device
04/06/2006US20060073698 Plasma enhanced nitride layer
04/06/2006US20060073697 Method for improving low-K dielectrics by supercritical fluid treatments
04/06/2006US20060073696 Semiconductor device and manufacturing method thereof
04/06/2006US20060073695 Gas dielectric structure forming methods
04/06/2006US20060073694 Method for isolating semiconductor device structures and structures thereof
04/06/2006US20060073693 Redistribution layer of wafer and the fabricating method thereof
04/06/2006US20060073692 Method for forming an electrode
04/06/2006US20060073691 Methods of manufacturing a semiconductor device
04/06/2006US20060073690 Apparatus and method for metal plasma vapor deposition and re-sputter with source and bias power frequencies applied through the workpiece
04/06/2006US20060073689 Method for fabricating doped polysilicon lines
04/06/2006US20060073688 Gate stacks
04/06/2006US20060073687 Method for maskless fabrication of self-aligned structures comprising a metal oxide
04/06/2006US20060073686 Method and system for reducing the impact of across-wafer variations on critical dimension measurements
04/06/2006US20060073685 Method for implanting dopants within a substrate by tilting the substrate relative to the implant source
04/06/2006US20060073684 Method for fabricating a doped zone in a semiconductor body
04/06/2006US20060073683 Plasma immersion ion implantation process using a capacitively coupled plasma source having low dissociation and low minimum plasma voltage
04/06/2006US20060073682 Low-k dielectric material based upon carbon nanotubes and methods of forming such low-k dielectric materials
04/06/2006US20060073681 Nanoheteroepitaxy of Ge on Si as a foundation for group III-V and II-VI integration
04/06/2006US20060073680 Epitaxial growth of aligned algainn nanowires by metal-organic chemical vapor deposition
04/06/2006US20060073679 CVD doped structures
04/06/2006US20060073678 System and method for hydrogen exfoliation gettering
04/06/2006US20060073677 Wafer dividing method and dividing apparatus
04/06/2006US20060073676 Pre-process before cutting a wafer and method of cutting a wafer
04/06/2006US20060073675 Semiconductor device and method of manufacturing thereof
04/06/2006US20060073674 Strained gettering layers for semiconductor processes
04/06/2006US20060073673 Ammonium hydroxide treatments for semiconductor substrates
04/06/2006US20060073672 Integrated BiCMOS semiconductor circuit
04/06/2006US20060073671 Method of producing element separation structure
04/06/2006US20060073670 Method of manufacturing a semiconductor device
04/06/2006US20060073669 Method of manufacturing a semiconductor device
04/06/2006US20060073668 Production method for electric double-layer capacitor
04/06/2006US20060073667 Stabilized silver nanoparticles and their use
04/06/2006US20060073666 Non-volatile memory device with conductive sidewall spacer and method for fabricating the same
04/06/2006US20060073665 Source/drain extensions having highly activated and extremely abrupt junctions
04/06/2006US20060073664 Semiconductor device and manufacturing method of the same
04/06/2006US20060073663 Method of manufacturing semiconductor device
04/06/2006US20060073662 Method of manufacturing multi-channel transistor device and multi-channel transistor device manufactured using the method
04/06/2006US20060073661 Method for forming wall oxide layer and isolation layer in flash memory device
04/06/2006US20060073660 Method of manufacturing flash memory device
04/06/2006US20060073659 Method for fabricating a storage capacitor
04/06/2006US20060073658 Method for making a ferroelectric memory cell in a ferroelectric memory device, and a ferroelectric memory device
04/06/2006US20060073657 Junction diode comprising varying semiconductor compositions
04/06/2006US20060073656 Method and system for improved nickel silicide
04/06/2006US20060073655 Phase change memory with a select device having a breakdown layer
04/06/2006US20060073654 Maintenance system, substrate processing device, remote operation device, and communication method
04/06/2006US20060073653 Methods of fabricating flash memory devices with floating gates that have reduced seams
04/06/2006US20060073652 Phase change memory with ovonic threshold switch