Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
08/2006
08/15/2006US7091453 Heat treatment apparatus by means of light irradiation
08/15/2006US7091443 Heating device and heating method
08/15/2006US7091377 Multimetal oxide materials
08/15/2006US7091295 Amorphous perfluorinated polymers
08/15/2006US7091294 Fluoropolymer and resist composition
08/15/2006US7091287 triazine-based molecules including linear organic molecules or polymers, crosslinked organic polymers, hyperbranched organic molecules or polymers, and/or dendrimer organic materials, thermolyzed at 200 to 450 degrees C.
08/15/2006US7091165 Composition and method for removing copper-compatible resist
08/15/2006US7091138 Forming method and a forming apparatus of nanocrystalline silicon structure
08/15/2006US7091137 Bi-layer approach for a hermetic low dielectric constant layer for barrier applications
08/15/2006US7091136 Method of forming semiconductor compound film for fabrication of electronic device and film produced by same
08/15/2006US7091135 Method of manufacturing semiconductor device
08/15/2006US7091134 Deposition of integrated circuit fabrication materials using a print head
08/15/2006US7091133 Two-step formation of etch stop layer
08/15/2006US7091132 Ultrasonic assisted etch using corrosive liquids
08/15/2006US7091131 Method of forming integrated circuit structures in silicone ladder polymer
08/15/2006US7091130 Method of forming a nanocluster charge storage device
08/15/2006US7091129 Atomic layer deposition using photo-enhanced bond reconfiguration
08/15/2006US7091128 Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs
08/15/2006US7091127 Methods and apparatus for patterning a surface
08/15/2006US7091126 Method for copper surface smoothing
08/15/2006US7091125 Method and apparatus for structuring electrodes for organic light-emitting display and organic light-emitting display manufactured using the method and apparatus
08/15/2006US7091124 Methods for forming vias in microelectronic devices, and methods for packaging microelectronic devices
08/15/2006US7091123 Method of forming metal wiring line including using a first insulating film as a stopper film
08/15/2006US7091122 Semiconductor device and method of manufacturing the same
08/15/2006US7091121 Bumping process
08/15/2006US7091120 System and process for producing nanowire composites and electronic substrates therefrom
08/15/2006US7091119 Encapsulated MOS transistor gate structures and methods for making the same
08/15/2006US7091118 Replacement metal gate transistor with metal-rich silicon layer and method for making the same
08/15/2006US7091117 Method of fabricating a semiconductor device
08/15/2006US7091116 Methods of manufacturing semiconductor devices
08/15/2006US7091115 Method for doping a semiconductor body
08/15/2006US7091114 Semiconductor device and method of manufacturing the same
08/15/2006US7091113 Methods of forming semiconductor constructions
08/15/2006US7091112 Method of forming a polycrystalline silicon layer
08/15/2006US7091110 Method of manufacturing a semiconductor device by gettering using a anti-diffusion layer
08/15/2006US7091109 Semiconductor device and method for producing the same by dicing
08/15/2006US7091108 Methods and apparatuses for manufacturing ultra thin device layers for integrated circuit devices
08/15/2006US7091107 Method for producing SOI wafer and SOI wafer
08/15/2006US7091106 Method of reducing STI divot formation during semiconductor device fabrication
08/15/2006US7091105 Method of forming isolation films in semiconductor devices
08/15/2006US7091104 Shallow trench isolation
08/15/2006US7091103 TEOS assisted oxide CMP process
08/15/2006US7091102 Methods of forming integrated circuit devices having a capacitor with a hydrogen barrier spacer on a sidewall thereof and integrated circuit devices formed thereby
08/15/2006US7091101 Method of forming a device
08/15/2006US7091100 Polysilicon bipolar transistor and method of manufacturing it
08/15/2006US7091099 Bipolar transistor and method for fabricating the same
08/15/2006US7091098 Semiconductor device with spacer having batch and non-batch layers
08/15/2006US7091097 End-of-range defect minimization in semiconductor device
08/15/2006US7091096 Method of fabricating carbon nanotube field-effect transistors through controlled electrochemical modification
08/15/2006US7091095 Dual strain-state SiGe layers for microelectronics
08/15/2006US7091094 Method of making a semiconductor device having a gate electrode with an hourglass shape
08/15/2006US7091093 Method for fabricating a semiconductor device having a pocket dopant diffused layer
08/15/2006US7091092 Process flow for a performance enhanced MOSFET with self-aligned, recessed channel
08/15/2006US7091091 Nonvolatile memory fabrication methods in which a dielectric layer underlying a floating gate layer is spaced from an edge of an isolation trench and/or an edge of the floating gate layer
08/15/2006US7091090 Nonvolatile memory device and method of forming same
08/15/2006US7091089 Method of forming a nanocluster charge storage device
08/15/2006US7091088 UV-blocking etch stop layer for reducing UV-induced charging of charge storage layer in memory devices in BEOL processing
08/15/2006US7091087 Optimized flash memory cell
08/15/2006US7091085 Reduced cell-to-cell shorting for memory arrays
08/15/2006US7091084 Ultra-high capacitance device based on nanostructures
08/15/2006US7091083 Method for producing a capacitor
08/15/2006US7091082 Semiconductor method and device
08/15/2006US7091081 Method for patterning a semiconductor region
08/15/2006US7091080 Depletion implant for power MOSFET
08/15/2006US7091079 Method of forming devices having three different operation voltages
08/15/2006US7091078 Selection of optimal quantization direction for given transport direction in a semiconductor device
08/15/2006US7091077 Method of directionally trimming polysilicon width
08/15/2006US7091076 Method for fabricating semiconductor device having first and second gate electrodes
08/15/2006US7091075 Fabrication of an EEPROM cell with SiGe source/drain regions
08/15/2006US7091074 Method of forming a gate oxide layer in a semiconductor device and method of forming a gate electrode having the same
08/15/2006US7091073 Semiconductor component, active matrix substrate for a liquid crystal display, and methods of manufacturing such component and substrate
08/15/2006US7091072 Semiconductor device and method for manufacturing the same
08/15/2006US7091071 Semiconductor fabrication process including recessed source/drain regions in an SOI wafer
08/15/2006US7091070 Semiconductor device and method of manufacturing the same
08/15/2006US7091069 Ultra thin body fully-depleted SOI MOSFETs
08/15/2006US7091068 Planarizing sacrificial oxide to improve gate critical dimension in semiconductor devices
08/15/2006US7091067 Current limiting antifuse programming path
08/15/2006US7091066 Method of making circuitized substrate
08/15/2006US7091065 Method of making a center bond flip chip semiconductor carrier
08/15/2006US7091064 Method and apparatus for attaching microelectronic substrates and support members
08/15/2006US7091063 Electronic assembly comprising solderable thermal interface and methods of manufacture
08/15/2006US7091062 Wafer level packages for chips with sawn edge protection
08/15/2006US7091061 Method of forming a stack of packaged memory dice
08/15/2006US7091060 Circuit and substrate encapsulation methods
08/15/2006US7091059 Method of forming a photosensor comprising a plurality of trenches
08/15/2006US7091058 Sacrificial protective layer for image sensors and method of using
08/15/2006US7091057 Method of making a single-crystal-silicon 3D micromirror
08/15/2006US7091056 Method of manufacturing a semiconductor light emitting device, semiconductor light emitting device, method of manufacturing a semiconductor device, semiconductor device, method of manufacturing a device, and device
08/15/2006US7091055 White light emitting diode and method for manufacturing the same
08/15/2006US7091054 Manufacturing method for emitter for electron-beam projection lithography
08/15/2006US7091053 In-line wafer surface mapping
08/15/2006US7091052 Method of forming ferroelectric memory cell
08/15/2006US7090967 Coating substrate with photoresist; selectively exposure, development, and removal; coating to smoothen roughness; crosslinking; integrated circuits
08/15/2006US7090966 Variations in the accumulated illumination intensity of radiation on the surface of the plate are controlled to 20% or less, thus alleviating unevenness of distribution of energy to be irradiated on the plate; forming a conductive film by discharging a liquid material using an ink-jet
08/15/2006US7090965 Method for enhancing adhesion between reworked photoresist and underlying oxynitride film
08/15/2006US7090963 Process for forming features of 50 nm or less half-pitch with chemically amplified resist imaging
08/15/2006US7090960 Photoresists comprising mixtures of alkali soluble copolymers, curing agents and acid generators, having high sensitivity and resolution, for use in microstructure lithography
08/15/2006US7090949 Method of manufacturing a photo mask and method of manufacturing a semiconductor device
08/15/2006US7090947 Phase shifter film and process for the same
08/15/2006US7090932 base material with coating layer made predominantly of yttrium oxide having a thickness of 10 mu m or more; yttrium oxide of coating layer contains solid solution silicon ranging from 100 ppm to 1000 ppm; uniform thermal spray