Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
02/2007
02/13/2007US7176097 Semiconductor device and process of fabricating same
02/13/2007US7176096 Transistor gate and local interconnect
02/13/2007US7176095 Bi-modal halo implantation
02/13/2007US7176094 Ultra-thin gate oxide through post decoupled plasma nitridation anneal
02/13/2007US7176093 Semiconductor processing methods of forming integrated circuitry
02/13/2007US7176092 Gate electrode for a semiconductor fin device
02/13/2007US7176091 Drain-extended MOS transistors and methods for making the same
02/13/2007US7176090 Method for making a semiconductor device that includes a metal gate electrode
02/13/2007US7176089 Vertical dual gate field effect transistor
02/13/2007US7176088 Bitline structure and method for production thereof
02/13/2007US7176087 Methods of forming electrical connections
02/13/2007US7176086 Interconnecting conductive layers of memory devices
02/13/2007US7176085 Method of manufacturing split gate type nonvolatile memory device
02/13/2007US7176084 Self-aligned conductive spacer process for sidewall control gate of high-speed random access memory
02/13/2007US7176083 High write and erase efficiency embedded flash cell
02/13/2007US7176082 Analog capacitor in dual damascene process
02/13/2007US7176081 Low temperature method for metal deposition
02/13/2007US7176080 Method of fabricating semiconductor device
02/13/2007US7176079 Method of fabricating a semiconductor device with a wet oxidation with steam process
02/13/2007US7176078 Nonvolatile semiconductor memory device having strap region and fabricating method thereof
02/13/2007US7176077 Methods of forming memory cells and arrays having underlying source-line connections
02/13/2007US7176076 Semiconductor CMOS devices and methods with NMOS high-k dielectric present in core region that mitigate damage to dielectric materials
02/13/2007US7176075 Field effect transistor and method of fabrication
02/13/2007US7176074 Manufacturing method of thin film transistor array substrate
02/13/2007US7176073 Methods of forming memory cells having diodes and electrode plates connected to source/drain regions
02/13/2007US7176072 Strained silicon devices transfer to glass for display applications
02/13/2007US7176071 Semiconductor device and fabrication method with etch stop film below active layer
02/13/2007US7176070 Active matrix organic light emitting display and method of forming the same
02/13/2007US7176069 Manufacture method of display device
02/13/2007US7176068 Semiconductor device and manufacturing method thereof
02/13/2007US7176067 Methods of fabricating fin field effect transistors
02/13/2007US7176066 Fabrication of nanoelectronic circuits
02/13/2007US7176065 Magnetic tunneling junction antifuse device
02/13/2007US7176064 Memory cell comprising a semiconductor junction diode crystallized adjacent to a silicide
02/13/2007US7176063 High density 3-D integrated circuit package
02/13/2007US7176062 Lead-frame method and assembly for interconnecting circuits within a circuit module
02/13/2007US7176061 Semiconductor device and method for manufacturing the same
02/13/2007US7176060 Integrated circuit card and a method of manufacturing the same
02/13/2007US7176059 Method of fabricating an electronic component having at least one semiconductor chip on a circuit carrier with elastic external contacts
02/13/2007US7176058 Chip scale package and method of fabricating the same
02/13/2007US7176057 Power module comprising at least two substrates and method for producing the same
02/13/2007US7176056 Semiconductor integrated circuit device and method of manufacturing the same
02/13/2007US7176055 Method and apparatus for manufacturing electronic component-mounted component, and electronic component-mounted component
02/13/2007US7176054 Method of forming a p-type group II-VI semiconductor crystal layer on a substrate
02/13/2007US7176052 Capacitor, circuit board, method of formation of capacitor, and method of production of circuit board
02/13/2007US7176051 Method of reducing charging damage to integrated circuits during semiconductor manufacturing
02/13/2007US7176049 Method of increasing a free carrier concentration in a semiconductor substrate
02/13/2007US7176048 Optically coupled sealed-cavity resonator and process
02/13/2007US7176047 Method for manufacturing MEMS structures
02/13/2007US7176046 Apparatus and a method of fabricating inversion channel devices with precision gate doping for a monolithic integrated circuit
02/13/2007US7176045 Laser diode operable in 1.3 μm or 1.5 μm wavelength band with improved efficiency
02/13/2007US7176044 For connecting microelectronic circuitry
02/13/2007US7176043 Microelectronic packages and methods therefor
02/13/2007US7176042 Laser beam irradiation method that includes determining a thickness of semiconductor prior to crystallizing
02/13/2007US7176041 PAA-based etchant, methods of using same, and resultant structures
02/13/2007US7176040 Inkjet-fabricated integrated circuits
02/13/2007US7176039 Dynamic modification of gap fill process characteristics
02/13/2007US7176038 Ferroelectric element and method for manufacturing the same
02/13/2007US7175974 applying mixtures of curing agents, light absorbers, acid generators, solvents and polydimethylsiloxane on the surfaces of a layer to be etched, then baking to form films, applying photosensitive materials, exposing to a light source and developing to form patterns
02/13/2007US7175970 Forming trench above via from photoresist trench pattern in dielectric layer; treating locally base portions by a post treatment using trench pattern as mask to enhance mechanical strength; depositing seed and barrier layers; filling
02/13/2007US7175963 Chemical amplification type positive resist composition and a resin therefor
02/13/2007US7175962 Incompletely oxidized transition metal having oxygen content lower than stoichiometric oxygen content; selectively exposed and developed to pattern; resolution
02/13/2007US7175960 Positive resist composition and patterning process
02/13/2007US7175952 Method of generating mask distortion data, exposure method and method of producing semiconductor device
02/13/2007US7175945 Phase shifting zones for separation of light source used to determine the quality of photolithographic prints
02/13/2007US7175943 Multilayer photomasking; circuit patterns; connecting opacity zones; adjustment of pattern using photomasking
02/13/2007US7175940 Generating photolithography masks; calibration patterns
02/13/2007US7175776 Method of fabricating a micro-electromechanical device with a thermal actuator
02/13/2007US7175775 Method of fabricating printhead IC using CTE matched wafer and sacrificial materials
02/13/2007US7175737 Electrostatic chucking stage and substrate processing apparatus
02/13/2007US7175728 Heat-peelable adhesive sheet
02/13/2007US7175714 Electrode-built-in susceptor and a manufacturing method therefor
02/13/2007US7175713 Apparatus for cyclical deposition of thin films
02/13/2007US7175706 Process of producing multicrystalline silicon substrate and solar cell
02/13/2007US7175705 Process for producing compound semiconductor single crystal
02/13/2007US7175704 Method for reducing defect concentrations in crystals
02/13/2007US7175680 Method to increase electromigration resistance of copper using self-assembled organic thiolate monolayers
02/13/2007US7175508 Polishing apparatus, method of manufacturing semiconductor device using the same, and semiconductor device manufactured by this method
02/13/2007US7175504 Vacuum suction holding apparatus and holding method, polishing apparatus using this holding apparatus, and device manufacturing method using this polishing apparatus
02/13/2007US7175405 Compression molding machine
02/13/2007US7175214 Wafer gripping fingers to minimize distortion
02/13/2007US7175024 Configurable insert for a manufacturing carrier
02/13/2007US7174631 Method of fabricating electrical connection terminal of embedded chip
02/13/2007US7174629 Integrated circuit contactor, and method and apparatus for production of integrated circuit contactor
02/13/2007US7174626 Method of manufacturing a plated electronic termination
02/08/2007WO2007016699A2 Method and system for debug and test using replicated logic
02/08/2007WO2007016689A1 Method and apparatus for in-line processing and immediately sequential or simultaneous processing of flat and flexible substrates through viscous shear in thin cross section gaps for the manufacture of micro-electronic circuits or displays
02/08/2007WO2007016514A2 Metal gate mosfet by full semiconductor metal alloy conversion
02/08/2007WO2007016477A2 Normally off iii-nitride semiconductor device having a programmable gate
02/08/2007WO2007016453A2 Systems and methods for capture substrates
02/08/2007WO2007016446A2 Dielectric isolated body biasing of silicon on insulator
02/08/2007WO2007016196A2 Directed purge for contact free drying of wafers
02/08/2007WO2007016193A2 Nanoparticle synthesis and associated methods
02/08/2007WO2007016080A2 Silicon nanoparticle formation from silicon powder and hexacholorplatinic acid
02/08/2007WO2007016036A1 Plastic semiconductor package having improved control of dimensions
02/08/2007WO2007016003A1 Bonding surfaces together via plasma treatment on both surfaces with wet treatment on only one surface
02/08/2007WO2007015987A2 System and method for improving mesa width in a semiconductor device
02/08/2007WO2007015975A2 Process for determining the actual position of a rotation axis of a transportation mechanism
02/08/2007WO2007015965A2 Semiconductor die attachment for high vacuum tubes
02/08/2007WO2007015957A2 Virtual body-contacted trigate