Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
04/2007
04/19/2007WO2006026701A3 Tripled-gate transistor segment with engineered corners
04/19/2007WO2005122243A3 Method and apparatus for cleaving brittle materials
04/19/2007WO2005112113A3 Mounting with auxiliary bumps
04/19/2007WO2005084175A3 Nanostructures, nanogrooves, and nanowires
04/19/2007US20070089081 Net/wiring selection method, net selection method, wiring selection method, and delay improvement method
04/19/2007US20070088450 Method of controlling substrate processing apparatus and substrate processing apparatus
04/19/2007US20070088144 Organic silicate polymer and insulation film comprising the same
04/19/2007US20070087671 Method of adhering polishing pads and jig for adhering the same
04/19/2007US20070087663 Polishing apparatus
04/19/2007US20070087646 Manufacturing method of organic electroluminescence display device
04/19/2007US20070087644 Method of producing image display unit
04/19/2007US20070087584 Plasma doping method and plasma doping apparatus for performing the same
04/19/2007US20070087583 Method of forming a silicon oxynitride layer
04/19/2007US20070087582 Gas jet reduction of iso-dense field thickness bias for gapfill process
04/19/2007US20070087581 Technique for atomic layer deposition
04/19/2007US20070087580 Composition for removing an insulation material, method of removing an insulation layer and method of recycling a substrate using the same
04/19/2007US20070087579 Semiconductor device manufacturing method
04/19/2007US20070087578 Ion beam sputtering apparatus and film deposition method for a multilayer for a reflective-type mask blank for EUV lithography
04/19/2007US20070087577 Barrier metal film production apparatus, barrier metal film production method, metal film production method, and metal film production apparatus
04/19/2007US20070087576 Substrate susceptor for receiving semiconductor substrates to be deposited upon
04/19/2007US20070087575 Method for fabricating silicon nitride spacer structures
04/19/2007US20070087574 Conformal doping apparatus and method
04/19/2007US20070087573 Pre-treatment method for physical vapor deposition of metal layer and method of forming metal silicide layer
04/19/2007US20070087572 Method and apparatus for the improvement of material/voltage contrast
04/19/2007US20070087571 Etching bias reduction
04/19/2007US20070087570 Planarization of a heteroepitaxial layer
04/19/2007US20070087569 Method for fabricating semiconductor device
04/19/2007US20070087568 Apparatus for etching wafer by single-wafer process and single wafer type method for etching wafer
04/19/2007US20070087567 Physical vapor deposition methods for forming hydrogen-stuffed trench liners for copper-based metallization, and resultant structures
04/19/2007US20070087566 Controlled electroless plating
04/19/2007US20070087565 Methods of forming isolation regions and structures thereof
04/19/2007US20070087564 Method of forming an electronic device
04/19/2007US20070087563 Zirconium-doped tantalum oxide films
04/19/2007US20070087562 Method of fabricating semiconductor device by exposing upper sidewalls of contact plug to form charge storage electrode
04/19/2007US20070087561 Method for making an opening for electrical contact by etch back profile control
04/19/2007US20070087560 Method of manufacturing semiconductor device
04/19/2007US20070087559 Semiconductor device manufacturing method
04/19/2007US20070087558 Semiconductor device having isolation pattern in interlayer insulating layer between capacitor contact plugs and methods of fabricating the same
04/19/2007US20070087557 Semiconductor device with a toroidal-like junction
04/19/2007US20070087556 Method and mesh reference structures for implementing Z-axis cross-talk reduction through copper sputtering onto mesh reference planes
04/19/2007US20070087555 Increasing electromigration lifetime and current density in ic using vertically upwardly extending dummy via
04/19/2007US20070087554 Interconnection structure with low dielectric constant
04/19/2007US20070087553 Semiconductor Component And Method For Contracting Said Semiconductor Component
04/19/2007US20070087552 Method for simulating the movement of particles
04/19/2007US20070087551 Sacrificial inorganic polymer intermetal dielectric damascene wire and via liner
04/19/2007US20070087550 Low-voltage single-layer polysilicon eeprom memory cell
04/19/2007US20070087549 Method of manufacturing a wire grid polarizer
04/19/2007US20070087548 Method for forming bumps
04/19/2007US20070087547 Wafer structure with electroless plating metal connecting layer and method for fabricating the same
04/19/2007US20070087546 Etchant and method for forming bumps
04/19/2007US20070087545 Method of manufacturing image display device
04/19/2007US20070087544 Method for forming improved bump structure
04/19/2007US20070087543 Fuse structure having reduced heat dissipation towards the substrate
04/19/2007US20070087542 Method of forming a silicide
04/19/2007US20070087541 Method and apparatus for deposition & formation of metal silicides
04/19/2007US20070087540 Transistor having high mobility channel and methods
04/19/2007US20070087539 Method for manufacturing compound semiconductor epitaxial substrate
04/19/2007US20070087538 Method of manufacturing nand flash memory device
04/19/2007US20070087537 Manufacturing method of semiconductor device
04/19/2007US20070087536 Mosfet structure with multiple self-aligned silicide contacts
04/19/2007US20070087535 Semiconductor device
04/19/2007US20070087534 Electro-optical device, method of manufacturing the same, electronic apparatus, and semiconductor device
04/19/2007US20070087533 Gas ring and method of processing substrates
04/19/2007US20070087532 Method for applying a structure of joining material to the back surfaces of semiconductor chips
04/19/2007US20070087531 Method and apparatus for flag-less water bonding tool
04/19/2007US20070087530 Detection of seed layers on a semiconductor device
04/19/2007US20070087529 Simulation method of wafer warpage
04/19/2007US20070087528 Method and structure for vertically-stacked device contact
04/19/2007US20070087527 Method and device for bonding wafers
04/19/2007US20070087526 Method of recycling an epitaxied donor wafer
04/19/2007US20070087525 Method and apparatus for making coplanar isolated regions of different semiconductor materials on a substrate
04/19/2007US20070087524 Wafer singulation process
04/19/2007US20070087523 Recessed shallow trench isolation
04/19/2007US20070087522 Dielectric Gap Fill With Oxide Selectively Deposited Over Silicon Liner
04/19/2007US20070087521 Fabrication method of semiconductor device
04/19/2007US20070087520 Method for manufacturing semiconductor device
04/19/2007US20070087519 Method and structure for double lining for shallow trench isolation
04/19/2007US20070087518 Semiconductor device and method for producing the same
04/19/2007US20070087517 Method of manufacturing semiconductor device
04/19/2007US20070087516 Method for forming an isolating trench with a dielectric material
04/19/2007US20070087515 Low stress STI films and methods
04/19/2007US20070087514 SOI substrate with selective oxide layer thickness control
04/19/2007US20070087513 Method for forming a variable capacitor
04/19/2007US20070087512 Substrate embedded with passive device
04/19/2007US20070087511 Method for forming an avalanche photodiode
04/19/2007US20070087510 Semiconductor devices and manufacturing methods of the same
04/19/2007US20070087509 Semiconductor device and method of manufacturing the same
04/19/2007US20070087508 Method for making a p-i-n diode crystallized adjacent to a silicide in series with a dielectric antifuse
04/19/2007US20070087507 Crystalline-type device and approach therefor
04/19/2007US20070087506 Method of forming a semiconductor device
04/19/2007US20070087505 Method of forming a semiconductor device
04/19/2007US20070087504 Integration process flow for flash devices with low gap fill aspect ratio
04/19/2007US20070087503 Improving NROM device characteristics using adjusted gate work function
04/19/2007US20070087502 Method of forming FLASH cell array having reduced word line pitch
04/19/2007US20070087501 Semiconductor device and manufacturing method thereof
04/19/2007US20070087500 Semiconductor device and method of manufacturing the same
04/19/2007US20070087499 Semiconductor memory device with vertical channel transistor and method of fabricating the same
04/19/2007US20070087498 Methods of forming buried bit line DRAM circuitry
04/19/2007US20070087497 Electrically erasable programmable read-only memory cell and memory device and manufacturing method thereof
04/19/2007US20070087496 Non-volatile memory devices including fuse covered field regions