Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
05/2007
05/15/2007US7217992 Semiconductor device, semiconductor wafer, semiconductor module, and a method of manufacturing semiconductor device
05/15/2007US7217990 Tape package having test pad on reverse surface and method for testing the same
05/15/2007US7217989 Composition for selectively polishing silicon nitride layer and polishing method employing it
05/15/2007US7217988 Bipolar transistor with isolation and direct contacts
05/15/2007US7217987 Semiconductor device and manufacturing the same
05/15/2007US7217986 Method for modifying the impedance of semiconductor devices using a focused heating source
05/15/2007US7217985 Semiconductor device including a transistor having low threshold voltage and high breakdown voltage
05/15/2007US7217984 Divided drain implant for improved CMOS ESD performance
05/15/2007US7217981 Tunable temperature coefficient of resistance resistors and method of fabricating same
05/15/2007US7217979 Semiconductor apparatus including a radiator for diffusing the heat generated therein
05/15/2007US7217977 Covert transformation of transistor properties as a circuit protection method
05/15/2007US7217976 Low temperature process and structures for polycide power MOSFET with ultra-shallow source
05/15/2007US7217975 Lateral type semiconductor device
05/15/2007US7217974 Output prediction logic circuits with ultra-thin vertical transistors and methods of formation
05/15/2007US7217973 Semiconductor device including sidewall floating gates
05/15/2007US7217972 Semiconductor device
05/15/2007US7217971 Miniaturized semiconductor device with improved dielectric properties
05/15/2007US7217970 Devices containing platinum-iridium films and methods of preparing such films and devices
05/15/2007US7217969 Flip FERAM cell and method to form same
05/15/2007US7217967 CMOS image sensor and method for manufacturing the same
05/15/2007US7217965 Semiconductor device including fuse elements and bonding pad
05/15/2007US7217963 Semiconductor integrated circuit device
05/15/2007US7217954 Silicon carbide semiconductor device and method for fabricating the same
05/15/2007US7217953 Technique for suppression of edge current in semiconductor devices
05/15/2007US7217952 Method of manufacturing a semiconductor device and semiconductor manufacturing apparatus
05/15/2007US7217950 Insulated gate tunnel-injection device having heterojunction and method for manufacturing the same
05/15/2007US7217948 Semiconductor substrate
05/15/2007US7217946 Method for making a wire nanostructure in a semiconductor film
05/15/2007US7217945 Method to selectively increase the top resistance of the lower programming electrode in a phase-change memory cell and structures obtained thereby
05/15/2007US7217942 Plasma leak monitoring method, plasma processing apparatus and plasma processing method
05/15/2007US7217939 Capillary tubing
05/15/2007US7217934 Wafer scanning device
05/15/2007US7217923 Microstructured pattern inspection method
05/15/2007US7217915 Method and apparatus for detecting the position of light which is incident to a semiconductor die
05/15/2007US7217890 Method for fabricating a through-hole interconnection substrate and a through-hole interconnection substrate
05/15/2007US7217888 Electronic parts packaging structure and method of manufacturing the same
05/15/2007US7217887 Power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device
05/15/2007US7217670 Heating a treatment chamber to a process temperature;subsequently establishing a substantially steady state thermal condition in the treatment chamber by subjecting a series of semiconductor substrates to a semiconductor fabrication
05/15/2007US7217669 Method of forming a metal oxide film
05/15/2007US7217668 Gate technology for strained surface channel and strained buried channel MOSFET devices
05/15/2007US7217667 Processes for forming electronic devices including a semiconductor layer
05/15/2007US7217666 Reactive ion milling/RIE assisted CMP
05/15/2007US7217665 Method of plasma etching high-K dielectric materials with high selectivity to underlying layers
05/15/2007US7217663 Via hole and trench structures and fabrication methods thereof and dual damascene structures and fabrication methods thereof
05/15/2007US7217662 Method of processing a substrate
05/15/2007US7217661 Small grain size, conformal aluminum interconnects and method for their formation
05/15/2007US7217660 Method for manufacturing a semiconductor component that inhibits formation of wormholes
05/15/2007US7217659 Process for producing materials for electronic device
05/15/2007US7217658 Process modulation to prevent structure erosion during gap fill
05/15/2007US7217657 Semiconductor device having different metal silicide portions and method for fabricating the semiconductor device
05/15/2007US7217656 Structure and method for bond pads of copper-metallized integrated circuits
05/15/2007US7217655 Electroplated CoWP composite structures as copper barrier layers
05/15/2007US7217654 Semiconductor device and method of manufacturing the same
05/15/2007US7217653 Interconnects forming method and interconnects forming apparatus
05/15/2007US7217652 Method of forming highly conductive semiconductor structures via plasma etch
05/15/2007US7217651 Interconnects with interlocks
05/15/2007US7217650 Metallic nanowire interconnections for integrated circuit fabrication
05/15/2007US7217649 System and method for stress free conductor removal
05/15/2007US7217648 Post-ESL porogen burn-out for copper ELK integration
05/15/2007US7217647 Structure and method of making a semiconductor integrated circuit tolerant of mis-alignment of a metal contact pattern
05/15/2007US7217646 Method for connecting an integrated circuit to a substrate and corresponding circuit arrangement
05/15/2007US7217645 Method for manufacturing semiconductor device and electronic device and method for calculating connection condition
05/15/2007US7217644 Method of manufacturing MOS devices with reduced fringing capacitance
05/15/2007US7217643 Semiconductor structures and methods for fabricating semiconductor structures comprising high dielectric constant stacked structures
05/15/2007US7217642 Mask for crystallizing polysilicon and a method for forming thin film transistor using the mask
05/15/2007US7217641 Pendeoepitaxial methods of fabricating gallium nitride semiconductor layers on sapphire substrates, and gallium nitride semiconductor structures fabricated thereby
05/15/2007US7217640 Semiconductor device and manufacturing method thereof
05/15/2007US7217639 Method of manufacturing a material compound wafer
05/15/2007US7217638 Wafer back surface treating method and dicing sheet adhering apparatus
05/15/2007US7217636 Semiconductor-on-insulator silicon wafer
05/15/2007US7217635 Process for preparing a bonding type semiconductor substrate
05/15/2007US7217634 Methods of forming integrated circuitry
05/15/2007US7217633 Methods for fabricating an STI film of a semiconductor device
05/15/2007US7217632 Isolation methods in semiconductor devices
05/15/2007US7217631 Semiconductor device and method for fabricating the device
05/15/2007US7217630 Methods of forming hafnium oxide
05/15/2007US7217629 Epitaxial imprinting
05/15/2007US7217628 High performance integrated vertical transistors and method of making the same
05/15/2007US7217627 Semiconductor devices having diffusion barrier regions and halo implant regions and methods of fabricating the same
05/15/2007US7217626 Transistor fabrication methods using dual sidewall spacers
05/15/2007US7217625 Method of fabricating a semiconductor device having a shallow source/drain region
05/15/2007US7217624 Non-volatile memory device with conductive sidewall spacer and method for fabricating the same
05/15/2007US7217623 Fin FET and method of fabricating same
05/15/2007US7217622 Semiconductor device and method of manufacturing the semiconductor device
05/15/2007US7217621 Self-aligned split-gate NAND flash memory and fabrication process
05/15/2007US7217620 Methods of forming silicon quantum dots and methods of fabricating semiconductor memory device using the same
05/15/2007US7217619 Method for fabricating memory components
05/15/2007US7217618 Semiconductor device and method for fabricating the same using damascene process
05/15/2007US7217617 Methods of forming a capacitor
05/15/2007US7217616 Non-volatile memory cell and method of forming the same
05/15/2007US7217615 Capacitor fabrication methods including forming a conductive layer
05/15/2007US7217614 Methods to form electronic devices and methods to form a material over a semiconductive substrate
05/15/2007US7217613 Low cost fabrication of high resistivity resistors
05/15/2007US7217612 Manufacturing method for a semiconductor device with reduced local current
05/15/2007US7217611 Methods for integrating replacement metal gate structures
05/15/2007US7217610 Method for fabricating a semiconductor product with a memory area and a logic area
05/15/2007US7217609 Semiconductor fabrication process, lateral PNP transistor, and integrated circuit
05/15/2007US7217608 CMOS with strained silicon channel NMOS and silicon germanium channel PMOS
05/15/2007US7217607 Method for manufacturing semiconductor integrated circuit device
05/15/2007US7217606 Method of forming vertical sub-micron CMOS transistors on (110), (111), (311), (511), and higher order surfaces of bulk, soi and thin film structures
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