Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
05/2007
05/16/2007CN1964073A A MOS resistor and its manufacture method
05/16/2007CN1964072A An asymmetric Schottky barrier MOS transistor and its manufacture method
05/16/2007CN1964068A A power semiconductor structure capable of reducing conduction resistance and its manufacture method
05/16/2007CN1964067A Thin film transistor substrate for display
05/16/2007CN1964066A Gate electrode and mos transistor including gate and method of fabricating the same
05/16/2007CN1964065A Pixel structure of active organic light-emitting diode and its manufacture method
05/16/2007CN1964064A Display device and manufacturing method of the same
05/16/2007CN1964060A Solid-state imaging device and method of manufacturing the same
05/16/2007CN1964057A Bipolar transistor and back-gated transistor structure and method
05/16/2007CN1964056A Array substrate for liquid crystal display device and method of fabricating the same
05/16/2007CN1964054A Flash memory device and method of fabricating the same
05/16/2007CN1964052A Semiconductor memory and method for manufacturing the same
05/16/2007CN1964051A A metal capacitor structure and its manufacture method
05/16/2007CN1964050A Non-volatile memory device and fabrication method thereof
05/16/2007CN1964049A A shallow ditch groove structure of CMOS and its manufacture method
05/16/2007CN1964047A Semiconductor device and method of fabricating the same
05/16/2007CN1964046A Semiconductor device and method for manufacturing the semiconductor device
05/16/2007CN1964045A Semiconductor structure and fabrication method thereof
05/16/2007CN1964044A A semiconductor structure and method to isolate one first circuit and one second circuit
05/16/2007CN1964042A A luminescent device and its manufacture method
05/16/2007CN1964038A A three-dimensional wafer stacking structure with post-and-beam construction and method to stack three-dimensional wafer
05/16/2007CN1964037A A stacking type semiconductor chip package
05/16/2007CN1964028A 散热器 Heat sink
05/16/2007CN1964024A A porous silicon chip and its preparing method
05/16/2007CN1964023A An array substrate of thin-film transistor and its manufacture method
05/16/2007CN1964022A Thin-film transistor substrate and its manufacture method
05/16/2007CN1964021A Method of manufacturing nand flash memory device
05/16/2007CN1964020A Fabrication method of semiconductor integrated circuit device and probe card
05/16/2007CN1964019A A method to fabricate high resistance value polysilicon resistance in high voltage IC
05/16/2007CN1964018A Semiconductor component manufacture method
05/16/2007CN1964017A Cu wiring formation method
05/16/2007CN1964016A A method to realize STI in high voltage IC
05/16/2007CN1964015A A method to improve STI morphology in high voltage MOS device
05/16/2007CN1964014A A method to reduce leakage of isolating edge of shallow ditch groove in the process flow of gate oxide growth
05/16/2007CN1964013A Disassembly method and reuse method of substrate mounting member
05/16/2007CN1964012A A test method to determine Schottky barrier height by measuring admittance
05/16/2007CN1964011A Apparatus and method for pressure bonding and method for manufacturing semiconductor device
05/16/2007CN1964010A Electrical interconnection structure formation
05/16/2007CN1964009A A stand of wire loop
05/16/2007CN1964008A A processing technique for moisture-proof insulation of preamplifier
05/16/2007CN1964007A A method to manufacture packaging structure of 'L' shaped electric connection wafer level chip size
05/16/2007CN1964006A Method for fabricating a multilayer wiring board, multilayer wiring board, and electronic device using the same
05/16/2007CN1964005A A method to manufacture thin-film transistor
05/16/2007CN1964004A A method to improve isolation characteristic of high pressure NMOS part
05/16/2007CN1964003A A method to etch barrier layer of self-alignment refractory metal silicide
05/16/2007CN1964002A Method for fabricating controlled stress silicon nitride films
05/16/2007CN1964001A A method to generate super thin oxide layer with ozone water
05/16/2007CN1964000A A method to eliminate silicon nitride at the back of silicon chip
05/16/2007CN1963999A Method for forming trench using hard mask with high selectivity and isolation method for semiconductor device using the same
05/16/2007CN1963998A Semiconductor device, substrate of the same, and manufacturing method of the same, and liquid crystal display and manufacturing method of the same
05/16/2007CN1963997A A technique to generate mixed allotropic structure of VO2 film on Si base
05/16/2007CN1963996A A method for orientation growth of VO2 film of pulse laser deposition Si base
05/16/2007CN1963995A Processing method and semiconductor manufacturing method
05/16/2007CN1963994A Processing method and semiconductor manufacturing method
05/16/2007CN1963993A Method and apparatus for storing circuit calibration information
05/16/2007CN1963992A Substrate treating apparatus
05/16/2007CN1963991A A method to eliminate residual glue on semiconductor component and its special device
05/16/2007CN1963825A Opc trimming for performance
05/16/2007CN1963679A Alignment mark structure for aligning wafer
05/16/2007CN1963678A Method for limiting pattern
05/16/2007CN1963675A Infiltrating type micro-image apparatus and process thereof
05/16/2007CN1963674A Improved infiltrating type micro-image system with wafer sealing structure and method thereof
05/16/2007CN1963673A Infiltrating type micro-image exposal apparatus and method thereof
05/16/2007CN1963666A Method for fabricating integrated circuit features
05/16/2007CN1963651A Array base plate of thin film transistor of LCD and manufacturing method of the same
05/16/2007CN1963649A Thin film transistor array panel for liquid crystal display
05/16/2007CN1963616A Display and its manufacturing method
05/16/2007CN1963614A Array substrate for liquid crystal display device and method of fabricating the same
05/16/2007CN1963612A Display of initiative irradiance and passiveness reflection and manufacturing method thereof
05/16/2007CN1963548A Inspection method and device for semiconductor equipment
05/16/2007CN1963484A Phosphorus-doped amorphous diamond film electrode and preparation method of the same
05/16/2007CN1962960A Method for electrophoretic anode deposition preparation of carbon nanotube field-emission film
05/16/2007CN1962936A Method of direct deposition of polycrystalline silicon
05/16/2007CN1962934A Method of fabricating a silicon nitride stack
05/16/2007CN1962798A Epoxy resin adhesive composition and optical semiconductor adhesive adopting same
05/16/2007CN1962211A Substrate cutting device
05/16/2007CN1316860C Metal-containing resin particle, resin particle, electronic circuit substrate, and method of producing electronic circuit
05/16/2007CN1316744C Antifuse reroute of dies
05/16/2007CN1316700C Nd2 YVO4 light waveguide film device on Sio2 Substrate and its prepn
05/16/2007CN1316697C Clamp for measuring laser chip and making method
05/16/2007CN1316638C Method for structuring on oxide layer applied to substrate material
05/16/2007CN1316631C Semiconductor device and its producing method
05/16/2007CN1316630C Semiconductor device and method for manufacturing the same
05/16/2007CN1316629C Semiconductor device and its mfg. method
05/16/2007CN1316626C SOI semiconductor device and method for making same
05/16/2007CN1316625C Non-volatile memory and method of forming thereof
05/16/2007CN1316624C Semiconductor device and method for fabricating the same
05/16/2007CN1316623C Nonvolatile semiconductor memory device
05/16/2007CN1316622C Non-volatile memory and method for manufacturing the same
05/16/2007CN1316621C Complementary metal oxide semiconductor phase reverser
05/16/2007CN1316620C 半导体芯片 Semiconductor chip
05/16/2007CN1316619C Internal power for IC with temp. compensating pedestal generator
05/16/2007CN1316618C Semiconductor device, electrostatic discharging protection device and its making method
05/16/2007CN1316617C 集成电路 IC
05/16/2007CN1316616C Design of lithography alignment and overlay measurement marks on CMP finished damascene surface
05/16/2007CN1316615C Integrated circuit and method for arranging integrated circuit electric bus grid
05/16/2007CN1316614C Semiconductor devices
05/16/2007CN1316613C Sandwich antireflection structural metal layer of semiconductor and making process thereof
05/16/2007CN1316611C Wafer-level semiconductor package having lamination structure and making method thereof
05/16/2007CN1316610C Chip packaging structure and chip and subtrate electric connection structure