Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
06/2009
06/23/2009US7550366 Method for bonding substrates and device for bonding substrates
06/23/2009US7550365 Bonding structure and method of making
06/23/2009US7550364 Stress engineering using dual pad nitride with selective SOI device architecture
06/23/2009US7550363 Method of fabricating a semiconductor device having first and second trenches using non-concurrently formed hard mask patterns
06/23/2009US7550362 Method for manufacturing semiconductor device
06/23/2009US7550361 Trench structure and method for co-alignment of mixed optical and electron beam lithographic fabrication levels
06/23/2009US7550360 Solid electrolytic capacitor manufacturing method capable of easily and properly connecting anode electrode portion
06/23/2009US7550359 Methods involving silicon-on-insulator trench memory with implanted plate
06/23/2009US7550358 MEMS device including a laterally movable portion with piezo-resistive sensing elements and electrostatic actuating elements on trench side walls, and methods for producing the same
06/23/2009US7550357 Semiconductor device and fabricating method thereof
06/23/2009US7550356 Method of fabricating strained-silicon transistors
06/23/2009US7550355 Low-leakage transistor and manufacturing method thereof
06/23/2009US7550354 Nanoelectromechanical transistors and methods of forming same
06/23/2009US7550353 Method of forming semiconductor device
06/23/2009US7550352 MOS transistor having a recessed gate electrode and fabrication method thereof
06/23/2009US7550351 Structure and method for creation of a transistor
06/23/2009US7550350 Methods of forming flash memory device
06/23/2009US7550349 Method for forming gate dielectric layers
06/23/2009US7550348 Source side injection storage device with spacer gates and method therefor
06/23/2009US7550347 Methods of forming integrated circuit device gate structures
06/23/2009US7550346 Method for forming a gate dielectric of a semiconductor device
06/23/2009US7550345 Methods of forming hafnium-containing materials
06/23/2009US7550344 Semiconductor device and method for fabricating the same
06/23/2009US7550343 Forming a semiconductor structure in manufacturing a semiconductor device using one or more epitaxial growth processes
06/23/2009US7550342 Nonvolatile semiconductor memory device and method of manufacturing the same
06/23/2009US7550341 High density stepped, non-planar flash memory
06/23/2009US7550340 Silicon rich barrier layers for integrated circuit devices
06/23/2009US7550339 Memory device with high dielectric constant gate dielectrics and metal floating gates
06/23/2009US7550338 Method and structure for forming strained SI for CMOS devices
06/23/2009US7550337 Dual gate dielectric SRAM
06/23/2009US7550336 Method for fabricating an NMOS transistor
06/23/2009US7550334 Non-volatile memory and method of manufacturing the same
06/23/2009US7550333 Nonplanar device with thinned lower body portion and method of fabrication
06/23/2009US7550332 Non-planar transistor having germanium channel region and method of manufacturing the same
06/23/2009US7550331 Multi-channel type thin film transistor and method of fabricating the same
06/23/2009US7550330 Deep junction SOI MOSFET with enhanced edge body contacts
06/23/2009US7550329 Thin film transistor array panel and manufacturing method thereof
06/23/2009US7550328 Method for production of thin-film semiconductor device
06/23/2009US7550327 Method for fabricating thin film transistor substrate
06/23/2009US7550326 Method for manufacturing thin film device and semiconductor device
06/23/2009US7550325 Method of manufacturing an active matrix display device
06/23/2009US7550323 Electrical fuse with a thinned fuselink middle portion
06/23/2009US7550322 Manufacturing method for resin sealed semiconductor device
06/23/2009US7550321 Substrate having a functionally gradient coefficient of thermal expansion
06/23/2009US7550320 Method of fabricating substrate with embedded component therein
06/23/2009US7550319 Low temperature co-fired ceramic (LTCC) tape compositions, light emitting diode (LED) modules, lighting devices and method of forming thereof
06/23/2009US7550318 Interconnect for improved die to substrate electrical coupling
06/23/2009US7550317 Method for manufacture of wafer level package with air pads
06/23/2009US7550316 Board on chip package and manufacturing method thereof
06/23/2009US7550315 Method for fabricating semiconductor package with multi-layer die contact and external contact
06/23/2009US7550314 Patterned plasma treatment to improve distribution of underfill material
06/23/2009US7550313 Method for delineation of phase change memory (PCM) cells separated by PCM and upper electrode regions modified to have high film resistivity
06/23/2009US7550312 Image sensor
06/23/2009US7550311 Near-field optical probe based on SOI substrate and fabrication method thereof
06/23/2009US7550310 Techniques and systems for analyte detection
06/23/2009US7550309 Epitaxially growing a silicon/germanium layer on an SOI (Silicon On Insulator of buried oxide) wafer on a silicon support; enriching with germanium follwed by an oxidation/heat treatment; heating in argon/nitrogen to relax lattice; stress relieving; cost efficiency
06/23/2009US7550308 Transistor and display and method of driving the same
06/23/2009US7550307 Manufacturing method of TFD LCD panel
06/23/2009US7550306 Dual panel-type organic electroluminescent device and method for fabricating the same
06/23/2009US7550305 Method of forming light-emitting element
06/23/2009US7550304 Method for manufacturing semiconductor laser element
06/23/2009US7550303 Systems and methods for overlay shift determination
06/23/2009US7550253 Impervious barrier film includes an alkali-soluble addition polymer and a fluorine-based surface active agent; immersion photolithography using exposing light of a shorter wavelength, such as KrF or ArF excimer lasers, or F2 , ArKr, or Ar2 lasers; fine resist pattern; good shapes
06/23/2009US7550235 Applying optical proximity correction features to mask layouts using an interference map; computer software; applying the phase-balanced scattering bar (SB) features to a mask design based on the interference map associated with the given mask design utilizing a model-based approach
06/23/2009US7550180 utilizing glow discharge produced by supplying high-frequency power into an inside-evacuated reactor through a high-frequency power supply means to treat the surface of a treatment target substrate; good efficiency; low cost
06/23/2009US7550052 Method of producing a complex structure by assembling stressed structures
06/23/2009US7550046 Vapor deposition system using benzotriazole (BTA) and isopropyl alcohol for protecting copper interconnects
06/23/2009US7550043 Substrate processing method and substrate processing apparatus
06/23/2009US7550020 comprising cerium oxide abrasives, and cationic homo- or copolymer containing monomers of aminoalkyl group-containing (meth)acrylic ester or amide, aminoalkoxyalkyl group-containing (meth)acrylic ester; scratch resist; semiconductor production
06/23/2009US7549811 Substrate treating apparatus
06/23/2009US7549719 Method for the printing of homogeneous electronic material with a multi-ejector print head
06/23/2009US7549567 Component mounting tool, and method and apparatus for mounting component using this tool
06/23/2009US7549560 Wafer dividing method
06/23/2009US7549552 Storage container
06/23/2009US7549328 Method of fabricating a pressure sensor
06/23/2009CA2391911C Plasma processing apparatus with an electrically conductive wall
06/18/2009WO2009076661A2 Super-self-aligned contacts and method for making the same
06/18/2009WO2009076657A2 Modular flow cell and adjustment system
06/18/2009WO2009076534A1 Resonant body transistor and oscillator
06/18/2009WO2009076510A2 Semiconductor structure and method of manufacture
06/18/2009WO2009076509A2 Semiconductor structure and method of manufacture
06/18/2009WO2009076424A1 Composite coatings for whisker reduction
06/18/2009WO2009076414A2 Droplet actuator configurations and methods
06/18/2009WO2009076407A1 Techniques for reducing an electrical stress in an acceleration/deceleration system
06/18/2009WO2009076346A2 Lift pin for substrate processing
06/18/2009WO2009076299A2 Implementation of advanced endpoint functions within third party software by using a plug-in approach
06/18/2009WO2009076276A2 Systems and methods for delivery of fluid-containing process material combinations
06/18/2009WO2009076192A2 Mechanical memory transistor
06/18/2009WO2009076155A2 Particle trap
06/18/2009WO2009076076A2 Insulated gate e-mode transistors
06/18/2009WO2009076048A1 Method of forming a wire loop including a bend
06/18/2009WO2009076034A1 Method for testing a semiconductor device and a semiconductor device testing system
06/18/2009WO2009075970A1 Method for making structures with improved edge definition
06/18/2009WO2009075959A1 Method for forming high density patterns
06/18/2009WO2009075944A2 Improved solution deposition assembly
06/18/2009WO2009075810A2 Avoiding floating diffusion contamination
06/18/2009WO2009075756A2 Forming thin film transistors using ablative films
06/18/2009WO2009075747A1 Wafer carrier with hub
06/18/2009WO2009075739A2 Forming thin film transistors using ablative films
06/18/2009WO2009075731A1 Method and apparatus for removing polymer from the wafer backside and edge