Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
06/2009
06/17/2009CN101461041A Semiconductor device manufacturing method, semiconductor manufacturing apparatus and storage medium
06/17/2009CN101461040A Wet etch suitable for creating square cuts in SI and resulting structures
06/17/2009CN101461039A Laser material processing method
06/17/2009CN101461038A Shower plate, plasma processing device using the same, plasma processing method and manufacturing method of electronic apparatus
06/17/2009CN101461037A Electrical components for microelectronic devices and methods of forming the same
06/17/2009CN101461036A Valve for preventing reverse-flow
06/17/2009CN101461035A Ejection unit for removing components from an essentially planar arrangement of components
06/17/2009CN101460833A Surface inspection device
06/17/2009CN101460002A Method and apparatus for producing uniform processing rates
06/17/2009CN101459318A Manufacturing method of nitride semiconductor device and nitride semiconductor device
06/17/2009CN101459227A Laminated structure, and manufacturing method, display device, and display unit employing same
06/17/2009CN101459215A Method for manufacturing gallium nitride single crystalline substrate using self-split
06/17/2009CN101459172A 半导体器件 Semiconductor devices
06/17/2009CN101459145A Production method for polycrystalline silicon membrane
06/17/2009CN101459144A Method for removing medium residual from stack type grid flash memory
06/17/2009CN101459143A A removing method for oxide-nitride-oxide and polycrystalline residual
06/17/2009CN101459142A Method for growing high voltage and low voltage devices in E2PROM
06/17/2009CN101459141A Built-in EEPROM process for protecting logic low voltage region by SiN
06/17/2009CN101459140A Embedded EEPROM process for increasing lateral wall width by SAB
06/17/2009CN101459139A Manufacturing process for charge trapping device
06/17/2009CN101459138A Manufacturing method for mask read only memory device
06/17/2009CN101459137A DRAM unit transistor device and method
06/17/2009CN101459136A CMOS transistor and manufacturing process thereof
06/17/2009CN101459135A Implementing method for slot type dual layer grid power MOS device construction
06/17/2009CN101459134A Grid and manufacturing method for transistor
06/17/2009CN101459133A Preparation for dual layer polycrystalline silicon self aligning grid structure
06/17/2009CN101459132A Manufacturing process for high voltage planar power MOS device
06/17/2009CN101459131A Manufacturing process for high voltage planar power MOS device
06/17/2009CN101459130A Parasitic vertical PNP and manufacturing process thereof in BiCMOS process
06/17/2009CN101459129A Self-aligning Schottky diode and corresponding resistor conversion memory production method
06/17/2009CN101459128A Multi-bit memory cell structure and method of manufacturing the same
06/17/2009CN101459127A Sensor module and method for manufacturing a sensor module
06/17/2009CN101459126A Semiconductor device and method of manufacturing the same
06/17/2009CN101459125A Connection pore forming method
06/17/2009CN101459124A Chemical mechanical grinding method and wafer cleaning method
06/17/2009CN101459123A Through hole and dual damascene structure forming method
06/17/2009CN101459122A Through hole forming method
06/17/2009CN101459121A Through hole and through hole forming method
06/17/2009CN101459120A Method for removing interconnecting metal layer surface oxidation membrane
06/17/2009CN101459119A Method for forming contact hole
06/17/2009CN101459118A Method for eliminating tungsten puncture in tungsten plugging production process
06/17/2009CN101459117A Semi-conductor device, shallow groove isolation construction forming method
06/17/2009CN101459116A Shallow groove isolation construction manufacturing method
06/17/2009CN101459115A Shallow groove isolation construction manufacturing method
06/17/2009CN101459114A Shallow groove isolation construction, forming method and grinding method
06/17/2009CN101459113A Shallow groove isolation region forming method
06/17/2009CN101459112A Shallow groove isolation process and shallow groove isolation construction
06/17/2009CN101459111A Shallow groove isolation region forming method and dielectric layer forming method
06/17/2009CN101459110A Shallow groove isolation region and forming method thereof
06/17/2009CN101459109A Method for preparing shallow groove isolation structure
06/17/2009CN101459108A Method for forming shallow groove isolation structure and etching method for forming shallow groove
06/17/2009CN101459107A Method for forming shallow groove isolation structure and etching
06/17/2009CN101459106A Forming method of shallow groove isolation structure
06/17/2009CN101459105A Manufacturing method for thin-film circuit or thin-film switch
06/17/2009CN101459104A Stage device
06/17/2009CN101459103A Stage apparatus
06/17/2009CN101459102A Wafer positioning method
06/17/2009CN101459101A Automatic conveying device for turnover type wafer
06/17/2009CN101459100A Automatic conveying device for compact wafer
06/17/2009CN101459099A Wafer kit, monitoring system and method for semi-conductor production process
06/17/2009CN101459098A Method and device for wafer optimized scheduling
06/17/2009CN101459097A Method for detecting whether through-hole blocking layer is penetrated
06/17/2009CN101459096A Method for wafer back flattening and method for enhancing wire width consistency of photo-etching process
06/17/2009CN101459095A Wafer on-line detection method and on-line detection device
06/17/2009CN101459094A Method for measuring thickness of hemi-spherical granule polycrystalline silicon layer
06/17/2009CN101459093A Method for verifying asymmetric high voltage field effect tube drifting region resistor
06/17/2009CN101459092A Screen mask, method for printing conductive bonding material, mounting method of mounting devices, and mounting substrate
06/17/2009CN101459091A Method of opening pad in semiconductor device
06/17/2009CN101459090A Method for forming solder extrusion on surface of electronic substrate
06/17/2009CN101459089A Transistor encapsulation method and construction, jumper wire board for tester table
06/17/2009CN101459088A Redistribution metal layer and manufacturing method for redistribution convex point
06/17/2009CN101459087A Redistribution metal wire and manufacturing method for redistribution convex point
06/17/2009CN101459086A Encapsulation method and encapsulation construction for organic light emitting display device
06/17/2009CN101459085A Method for preparing HfO2 nano crystal by electron-beam evaporation method
06/17/2009CN101459084A Plane double diffusion metal oxide semiconductor device and preparation method
06/17/2009CN101459083A PMOS transistor and forming method thereof
06/17/2009CN101459082A MOS transistor and forming method thereof
06/17/2009CN101459081A MOS transistor forming method
06/17/2009CN101459080A Method for preparing gallium nitride based field-effect transistor
06/17/2009CN101459079A Source forming method for transistor and source of transistor
06/17/2009CN101459078A Producing method for shallow junction in transistor device
06/17/2009CN101459077A Triode transistor and reference voltage source forming method
06/17/2009CN101459076A Preparation for SiGe HBT transistor
06/17/2009CN101459075A Metal silicide layer and manufacturing method for semi-conductor device
06/17/2009CN101459074A Etching method and dual damascene structure forming method
06/17/2009CN101459073A Method for etching bottom layer anti-reflection layer
06/17/2009CN101459072A Method for etching bottom layer anti-reflection layer and manufacturing wire laying slot
06/17/2009CN101459071A Method for removing silicon oxide layer on surface of silicon substrate and contact hole forming
06/17/2009CN101459070A Method for producing grid oxide layer
06/17/2009CN101459069A Manufacturing method for gate and semi-conductor device
06/17/2009CN101459068A Production method for metal silicide contact layer
06/17/2009CN101459067A Gate forming method
06/17/2009CN101459066A Gate, shallow slot isolation region forming method and flattening method for silicon base etching surface
06/17/2009CN101459065A Production method for floating gate of flash memory in grating
06/17/2009CN101459064A Forming method for lateral wall substrate
06/17/2009CN101459063A Manufacturing method for transistor shallow junction
06/17/2009CN101459062A Decoupled plasma nitride preparing process
06/17/2009CN101459061A Preparation for relaxation thin SiGe virtual substrate
06/17/2009CN101459060A Method for manufacturing semiconductor device
06/17/2009CN101459059A Glass passivating technique process for semi-conductor device with silicon large diameter round wafer
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