Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
07/2009
07/14/2009US7560792 Reliable high voltage gate dielectric layers using a dual nitridation process
07/14/2009US7560783 Metal-semiconductor contact, semiconductor component, integrated circuit arrangement and method
07/14/2009US7560779 Method for forming a mixed voltage circuit having complementary devices
07/14/2009US7560776 Semiconductor device, electronic apparatus, method of manufacturing semiconductor device, and method of manufacturing electronic apparatus
07/14/2009US7560772 Semiconductor integrated circuit device and manufacturing method thereof
07/14/2009US7560771 Insulated gate transistor
07/14/2009US7560766 Nonvolatile semiconductor memory
07/14/2009US7560763 Semiconductor device and method for fabricating the same
07/14/2009US7560760 Ferroelectric memory devices having expanded plate lines
07/14/2009US7560759 Semiconductor device and method of manufacturing the same
07/14/2009US7560756 Tri-gate devices and methods of fabrication
07/14/2009US7560753 Field effect transistor with thin gate electrode and method of fabricating same
07/14/2009US7560734 Semiconductor device and manufacturing method thereof
07/14/2009US7560725 Method for fabricating group III nitride compound semiconductors and group III nitride compound semiconductor devices
07/14/2009US7560723 Enhanced memory density resistance variable memory cells, arrays, devices and systems including the same, and methods of fabrication
07/14/2009US7560581 reaction of vapors of tungsten bis(alkylimide)bis(dialkylamide) and a Lewis base or hydrogen plasma; very uniform thickness and excellent step coverage; good electrical conductors; microelectronics; similarly depositing molybdenum nitride suitable for layers alternating with silicon in X-ray mirrors
07/14/2009US7560501 comprising epoxy and cyanate ester resins, flexibilizers comprises bis(2,3-epoxy-2-methylpropyl)ether, a polyphenylene ether and silicon carbide fillers, having a higher fracture toughness, low viscosity and freeze resistance, used in electronic packages
07/14/2009US7560397 Laser irradiation method and method of manufacturing a semiconductor device
07/14/2009US7560396 Material for electronic device and process for producing the same
07/14/2009US7560395 Atomic layer deposited hafnium tantalum oxide dielectrics
07/14/2009US7560394 Nanodots formed on silicon oxide and method of manufacturing the same
07/14/2009US7560393 Systems and methods of forming refractory metal nitride layers using disilazanes
07/14/2009US7560392 Electrical components for microelectronic devices and methods of forming the same
07/14/2009US7560391 Forming of trenches or wells having different destinations in a semiconductor substrate
07/14/2009US7560390 Multiple spacer steps for pitch multiplication
07/14/2009US7560389 Method for fabricating semiconductor element
07/14/2009US7560388 Self-aligned pitch reduction
07/14/2009US7560387 Opening hard mask and SOI substrate in single process chamber
07/14/2009US7560386 Method of manufacturing nonvolatile semiconductor memory device
07/14/2009US7560385 Etching systems and processing gas specie modulation
07/14/2009US7560384 Chemical mechanical polishing method
07/14/2009US7560383 Method of forming a thin layer and method of manufacturing a non-volatile semiconductor device using the same
07/14/2009US7560382 Embedded interconnects, and methods for forming same
07/14/2009US7560381 Technique for metal deposition by electroless plating using an activation scheme including a substrate heating process
07/14/2009US7560380 Chemical dissolution of barrier and adhesion layers
07/14/2009US7560379 Semiconductive device fabricated using a raised layer to silicide the gate
07/14/2009US7560378 Method for manufacturing semiconductor device
07/14/2009US7560377 Plasma processes for depositing low dielectric constant films
07/14/2009US7560376 Method for adjoining adjacent coatings on a processing element
07/14/2009US7560375 Gas dielectric structure forming methods
07/14/2009US7560374 Mold for forming conductive bump, method of fabricating the mold, and method of forming bump on wafer using the mold
07/14/2009US7560373 Low temperature solder metallurgy and process for packaging applications and structures formed thereby
07/14/2009US7560372 Process for making a semiconductor device having a roughened surface
07/14/2009US7560371 Methods for selectively filling apertures in a substrate to form conductive vias with a liquid using a vacuum
07/14/2009US7560370 Method for manufacturing semiconductor device
07/14/2009US7560369 Method of forming metal line in semiconductor device
07/14/2009US7560368 Insulated gate planar integrated power device with co-integrated Schottky diode and process
07/14/2009US7560367 Method for thermal processing with a RTP process using temperature spaces in radiation equilibrium
07/14/2009US7560366 Forming nucleating particles comprising gold on base substrate, forming nanowire growth-inhibiting layer on nucleating particle and contacting nucleating particle with precursor gas mixtures suitable for growth of silicon nanowires, whereby silicon nanowires are grown from side surface of particle
07/14/2009US7560365 Method of semiconductor thin film crystallization and semiconductor device fabrication
07/14/2009US7560364 Dislocation-specific lateral epitaxial overgrowth to reduce dislocation density of nitride films
07/14/2009US7560363 Manufacturing method for SIMOX substrate
07/14/2009US7560362 Cutting method for substrate
07/14/2009US7560361 Method of forming gate stack for semiconductor electronic device
07/14/2009US7560360 Methods for enhancing trench capacitance and trench capacitor
07/14/2009US7560359 Methods of forming asymmetric recesses and gate structures that fill such recesses and related methods of forming semiconductor devices that include such recesses and gate structures
07/14/2009US7560357 Method for creating narrow trenches in dielectric materials
07/14/2009US7560356 Fabrication method of trench capacitor
07/14/2009US7560355 Semiconductor wafer suitable for forming a semiconductor junction diode device and method of forming same
07/14/2009US7560354 Process of forming an electronic device including a doped semiconductor layer
07/14/2009US7560353 Methods of fabricating memory devices with memory cell transistors having gate sidewall spacers with different dielectric properties
07/14/2009US7560352 Selective deposition
07/14/2009US7560351 Integrated circuit arrangement with low-resistance contacts and method for production thereof
07/14/2009US7560350 Method for forming strained semiconductor device and method for forming source/drain region
07/14/2009US7560349 Semiconductor device and gate structure having a composite dielectric layer and methods of manufacturing the same
07/14/2009US7560348 Method for designing and manufacturing a PMOS device with drain junction breakdown point located for reduced drain breakdown voltage walk-in
07/14/2009US7560347 Methods for forming a wrap-around gate field effect transistor
07/14/2009US7560346 Semiconductor device and method of manufacturing the same
07/14/2009US7560345 Method of assessing potential for charging damage in integrated circuit designs and structures for preventing charging damage
07/14/2009US7560344 Semiconductor device having a pair of fins and method of manufacturing the same
07/14/2009US7560343 Manufacturing method of non-volatile memory
07/14/2009US7560342 Method of manufacturing a semiconductor device having a plurality of memory and non-memory devices
07/14/2009US7560341 Semiconductor device and manufacturing method therefor
07/14/2009US7560340 Method of manufacturing flash memory device
07/14/2009US7560339 Nonvolatile memory cell comprising a reduced height vertical diode
07/14/2009US7560338 Manufacturing method of non-volatile memory
07/14/2009US7560337 Programmable resistive RAM and manufacturing method
07/14/2009US7560336 DRAM layout with vertical FETs and method of formation
07/14/2009US7560335 Memory device transistors
07/14/2009US7560334 Method and system for incorporating high voltage devices in an EEPROM
07/14/2009US7560333 Capacitor in semiconductor device and method of manufacturing the same
07/14/2009US7560332 Integrated circuit capacitor structure
07/14/2009US7560331 Method for forming a silicided gate
07/14/2009US7560330 CMOS image sensor and method for manufacturing the same
07/14/2009US7560329 Semiconductor device and method for fabricating the same
07/14/2009US7560328 Strained Si on multiple materials for bulk or SOI substrates
07/14/2009US7560327 Method of fabricating semiconductor device with dual gate structure
07/14/2009US7560326 Silicon/silcion germaninum/silicon body device with embedded carbon dopant
07/14/2009US7560325 Methods of making lateral junction field effect transistors using selective epitaxial growth
07/14/2009US7560324 Drain extended MOS transistors and methods for making the same
07/14/2009US7560323 Compound semiconductor device and method of fabricating the same
07/14/2009US7560322 Method of making a semiconductor structure for high power semiconductor devices
07/14/2009US7560321 Crystallization method, thin film transistor manufacturing method, thin film transistor, display, and semiconductor device
07/14/2009US7560320 Nonvolatile semiconductor memory and a fabrication method for the same
07/14/2009US7560319 Method for fabricating a semiconductor device
07/14/2009US7560318 Process for forming an electronic device including semiconductor layers having different stresses
07/14/2009US7560317 Method of forming single crystalline silicon layer, structure including the same, and method of fabricating thin film transistor using the same
07/14/2009US7560316 Thin film transistor panel and manufacturing method thereof
07/14/2009US7560315 Manufacturing method for semiconductor device
07/14/2009US7560314 Method of fabricating an active array color filter structure for a liquid crystal display