Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 8 - Arrangements for selecting an address in a digital store
Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368)
05/2010
05/26/2010CN1509475B Memory device, motion vector detection device and motion compensation prediction coding device
05/26/2010CN101714402A Method for reducing leakage current of a memory and related device
05/26/2010CN101183558B Novel word-line driver
05/26/2010CN101051521B Integrated device
05/25/2010US7725706 Microprocessor boot-up controller, nonvolatile memory controller, and information processing system
05/25/2010US7724606 Interface circuit
05/25/2010US7724605 Clock-based data storage device, dual pulse generation device, and data storage device
05/20/2010US20100124141 Semiconductor memory device of dual-port type
05/20/2010US20100124138 Semiconductor memory device having variable-mode refresh operation
05/20/2010US20100124137 Voltage-controlled oscillator, phase-locked loop, and memory device
05/20/2010US20100124133 Replacing defective memory blocks in response to external addresses
05/20/2010US20100124132 Replacing defective columns of memory cells in response to external addresses
05/20/2010US20100124131 Delay adjustment device, semiconductor device and delay adjustment method
05/20/2010US20100124130 Method and Apparatus to Reduce Power Consumption by Transferring Functionality from Memory Components to a Memory Interface
05/20/2010US20100124129 Data writing apparatus and method for semiconductor integrated circuit
05/20/2010US20100124126 Erase voltage reduction in a non-volatile memory device
05/20/2010US20100124107 Nonvolatile memory device and method of operating the same
05/20/2010US20100124105 Variable resistance memory device and system
05/20/2010US20100124104 Memory device and writing method thereof
05/20/2010US20100124095 Floating Source Line Architecture for Non-Volatile Memory
05/19/2010EP2186093A1 Shared memory
05/19/2010CN1992075B Address converter semiconductor device and semiconductor memory device having the same
05/19/2010CN1975634B Adaptive throttling of memory accesses
05/19/2010CN101208666B Nanoscale interconnection interface and method
05/18/2010US7721041 PSRAM and method for operating thereof
05/18/2010US7719922 Address counter, semiconductor memory device having the same, and data processing system
05/18/2010US7719920 Synchronous global controller for enhanced pipelining
05/18/2010US7719919 Semiconductor memory device in which word lines are driven from either side of memory cell array
05/18/2010US7719918 Semiconductor memory device having input/output sense amplification circuit with reduced junction loading and circuit layout area
05/18/2010US7719891 Non-volatile memory device
05/14/2010WO2010053938A1 Non-binary decoder architecture and control signal logic for reduced circuit complexity
05/14/2010WO2010051623A1 A bridging device having a configurable virtual page size
05/13/2010US20100118639 Semiconductor memory apparatus
05/13/2010US20100118635 Semiconductor memory device and method for operating the same
05/13/2010US20100118633 Semiconductor memory device having dummy sense amplifiers and methods of utilizing the same
05/13/2010US20100118630 Method and Apparatus for Synchronizing Data From Memory Arrays
05/13/2010US20100118628 Memory circuit and tracking circuit thereof
05/13/2010US20100118626 Delay device for shifting phase of strobe signal
05/13/2010US20100118616 Semiconductor memory device
05/13/2010US20100118596 Embedded DRAM with bias-independent capacitance
05/13/2010US20100118593 Variable resistance memory device and system thereof
05/13/2010US20100118592 Nonvolatile semiconductor memory device and method of controlling the same
05/13/2010US20100118587 Resistive sense memory array with partial block update capability
05/13/2010US20100118586 Ferroelectric memory
05/13/2010US20100118579 Nand Based Resistive Sense Memory Cell Architecture
05/12/2010EP2183747A1 Memory with data control
05/12/2010CN1992073B Address decoder, storage device, processor device, and address decoding method
05/12/2010CN1845329B Layout structure in semiconductor memory device and layout method therefor
05/12/2010CN1841750B 半导体存储装置 The semiconductor memory device
05/12/2010CN1759448B Sense amplifier, storage apparatus and computer system comprising the same, and method thereof
05/11/2010US7716401 Memory module capable of improving the integrity of signals transmitted through a data bus and a command/address bus, and a memory system including the same
05/11/2010US7715273 Synchronous semiconductor device and data processing system including the same
05/11/2010US7715272 Semiconductor device having latency counter
05/11/2010US7715271 Using dedicated read output path to reduce unregistered read access time for a FPGA embedded memory
05/11/2010US7715270 Address synchronous circuit capable of reducing current consumption in DRAM
05/11/2010US7715269 Semiconductor memory device and semiconductor device comprising the same
05/06/2010US20100110819 Apparatus and Method for Placement of Boosting Cell With Adaptive Booster Scheme
05/06/2010US20100110818 Semiconductor device
05/06/2010US20100110817 Semiconductor device and refreshing method
05/06/2010US20100110813 Precharge control circuits and methods for memory having buffered write commands
05/06/2010US20100110812 Semiconductor device
05/06/2010US20100110810 Semiconductor memory device and system
05/06/2010US20100110809 Semiconductor memory device and system with redundant element
05/06/2010US20100110808 Semiconductor memory device and control method thereof
05/06/2010US20100110806 Semiconductor memory device
05/06/2010US20100110805 Semiconductor memory device
05/06/2010US20100110802 Semiconductor device
05/06/2010US20100110801 Semiconductor device
05/06/2010US20100110775 Word Line Voltage Control in STT-MRAM
05/06/2010US20100110771 Variable resistive memory
05/06/2010US20100110770 Variable Resistance Memory Devices Including Arrays of Different Sizes
05/06/2010US20100110769 Controlling a variable resistive memory wordline switch
05/06/2010US20100110763 Write Current Compensation Using Word Line Boosting Circuitry
05/06/2010US20100110751 Semiconductor storage device
05/06/2010US20100110750 Non-volatile semiconductor memory device
05/06/2010US20100110749 Semiconductor memory device having driver for compensating for parasitic resistance of data input-output pads
05/06/2010US20100110748 Hybrid volatile and non-volatile memory device
05/06/2010US20100110747 Semiconductor memory device
05/06/2010US20100110745 Switched interface stacked-die memory architecture
05/06/2010US20100109702 Semiconductor integrated circuits with power reduction mechanism
05/06/2010DE10304173B4 Halbleiterspeicherbaustein und ein zugehöriges Einschaltleseverfahren Semiconductor memory device and an associated Einschaltleseverfahren
05/05/2010CN1906697B Method for operating a data storage apparatus employing passive matrix addressing
05/05/2010CN1853238B Method and apparatus for implicit DRAM precharge
05/05/2010CN1343987B Semiconductor memory device and memory modulus and system adopting same
05/04/2010US7711511 Method and apparatus for automatically testing a railroad interlocking
05/04/2010US7710818 Semiconductor memory device having low jitter source synchronous interface and clocking method thereof
05/04/2010US7710817 Semiconductor memory device having a delay locked loop (DLL) and method for driving the same
05/04/2010US7710816 Memory access circuit
05/04/2010US7710815 Access unit for a static random access memory
05/04/2010US7710814 Fast read port for register file
05/04/2010US7710809 Self refresh operation of semiconductor memory device
05/04/2010US7710799 Circuit for generating data strobe in DDR memory device, and method therefor
05/04/2010US7710791 Input circuit of a non-volatile semiconductor memory device
05/04/2010US7710789 Synchronous address and data multiplexed mode for SRAM
05/04/2010US7709277 PAA-based etchant, methods of using same, and resultant structures
04/2010
04/29/2010WO2010047870A1 Two-phase clock-stalling technique for error detection and error correction
04/29/2010US20100103762 Memory device and method
04/29/2010US20100103761 Memory devices having redundant arrays for repair
04/29/2010US20100103760 Memory Power Management Systems and Methods
04/29/2010US20100103754 Circuit, system and method for controlling read latency
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