Patents
Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368)
02/2010
02/24/2010CN100592423C Methods and circuits for latency control in accessing memory devices
02/24/2010CN100592421C Semiconductor memory device having a global data bus
02/23/2010US7668039 Address counter, semiconductor memory device having the same, and data processing system
02/23/2010US7668038 Semiconductor memory device including a write recovery time control circuit
02/23/2010US7668037 Storage array including a local clock buffer with programmable timing
02/23/2010US7668036 Apparatus for controlling GIO line and control method thereof
02/23/2010US7668028 Dual in-line memory module, memory test system, and method for operating the dual in-line memory module
02/23/2010US7668026 Data I/O line control circuit and semiconductor integrated circuit having the same
02/23/2010US7667485 Semiconductor integrated circuits with power reduction mechanism
02/18/2010WO2010019868A1 Dual power scheme in memory circuit
02/18/2010WO2009142884A3 Memory devices, memory device constructions, constructions, memory device forming methods, current conducting devices, and memory cell programming methods
02/18/2010US20100042478 Providing Services From A Remote Computer System To A User Station Over A Communications Network
02/18/2010US20100039878 Circuit and method for generating data output control signal for semiconductor integrated circuit
02/18/2010US20100039877 External clock tracking pipelined latch scheme
02/18/2010US20100039875 Strobe Acquisition and Tracking
02/18/2010US20100039872 Dual Power Scheme in Memory Circuit
02/18/2010US20100039871 Semiconductor memory device and method with auxiliary i/o line assist circuit and functionality
02/18/2010US20100039870 Memory control circuit and semiconductor integrated circuit incorporating the same
02/18/2010US20100039866 Sensing of memory cells in a solid state memory device by fixed discharge of a bit line
02/18/2010US20100039864 Methods of erase verification for a flash memory device
02/18/2010US20100039860 Memory devices and methods of storing data on a memory device
02/18/2010DE10116327B4 Schaltungsanordnung zum Steuern der Wortleitungen einer Speichermatrix Circuitry for controlling the word lines of a memory matrix
02/18/2010CA2730457A1 Dual power scheme in memory circuit
02/17/2010CN100590734C Semiconductor memory device
02/16/2010US7664908 Semiconductor memory device and operating method of the same
02/16/2010US7663967 Semiconductor memory device having a plurality of chips and capability of outputting a busy signal
02/16/2010US7663966 Single-clock, strobeless signaling system
02/16/2010US7663965 Memory with clock-controlled memory access and method of operating the same
02/16/2010US7663964 Memory device, memory system and method of operating such
02/16/2010US7663963 Apparatus and method for providing multiple reads/writes using a 2Read/2Write register file array
02/16/2010US7663962 Semiconductor memory device
02/16/2010US7663961 Reduced-power memory with per-sector power/ground control and early address
02/16/2010US7663945 Semiconductor memory with a delay circuit
02/16/2010US7663943 Semiconductor memory device and method for reading/writing data thereof
02/16/2010US7663931 Word line driving method of semiconductor memory device
02/16/2010US7663392 Synchronous semiconductor device, and inspection system and method for the same
02/11/2010WO2010016879A1 Row mask addressing
02/11/2010WO2010016818A1 Independently controlled virtual memory devices in memory modules
02/11/2010WO2010016817A1 Independently controllable and reconfigurable virtual memory devices in memory modules that are pin-compatible with standard memory modules
02/11/2010US20100034045 Semiconductor memory and memory system
02/11/2010US20100034040 Semiconductor integrated circuit
02/11/2010US20100034038 Integrated circuit including selectable address and data multiplexing mode
02/11/2010US20100034036 Semiconductor integrated circuit device for controlling a sense amplifier
02/11/2010US20100034035 Address latch circuit and semiconductor memory apparatus using the same
02/11/2010US20100034015 Semiconductor device
02/11/2010DE10317162B4 Speichervorrichtung mit kurzer Wortleitungszykluszeit und Leseverfahren hierzu Storage device with a short word line cycle time and reading method therefor
02/09/2010US7660187 Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM
02/09/2010US7660186 Memory clock generator having multiple clock modes
02/09/2010US7660185 Chip select controller and non-volatile memory device including the same
02/09/2010US7660184 Semiconductor memory for disconnecting a bit line from a sense amplifier in a standby period and memory system including the semiconductor memory
02/09/2010US7660183 Low power memory device
02/09/2010US7660156 NAND flash memory with a programming voltage held dynamically in a NAND chain channel region
02/04/2010US20100027369 Semiconductor integrated circuit device
02/04/2010US20100027368 Read command triggered synchronization circuitry
02/04/2010US20100027367 Row mask addressing
02/04/2010US20100027364 Multi-port memory device having self-refresh mode
02/04/2010US20100027363 Refresh controller and refresh controlling method for embedded dram
02/04/2010US20100027359 Memory test circuit which tests address access time of clock synchronized memory
02/04/2010US20100027358 Semiconductor memory device capable of read out mode register information through DQ pads
02/04/2010US20100027354 Semiconductor memory device and method for testing same
02/04/2010US20100027338 Semiconductor device and a manufacturing method thereof
02/04/2010US20100027337 Nonvolatile memory device extracting parameters and nonvolatile memory system including the same
02/04/2010US20100027327 Nonvolatile Memory Devices Having Variable-Resistance Memory Cells and Methods of Programming the Same
02/04/2010US20100027320 Resistance variable element, resistance variable memory apparatus, and resistance variable apparatus
02/04/2010US20100027310 Apparatus and methods for optically-coupled memory systems
02/04/2010US20100025659 Non-volatile electromechanical field effect devices and circuits using same and methods of forming same
02/04/2010DE102008040794A1 Speicheranordnung und Speicherarchitektur Memory array and memory architecture
02/03/2010CN100587840C Memory device having delay locked loop
02/03/2010CN100587839C Storage for controlling address buffer by programmable delay
02/02/2010US7656745 Circuit, system and method for controlling read latency
02/02/2010US7656744 Memory module with load capacitance added to clock signal input
02/02/2010US7656743 Clock signal generation techniques for memories that do not generate a strobe
02/02/2010US7656742 Circuit and method for sampling valid command using extended valid address window in double pumped address scheme memory device
02/02/2010US7656740 Wordline voltage transfer apparatus, systems, and methods
02/02/2010US7656738 Nonvolatile semiconductor storage device having a low resistance write-bit-line and a low capacitance read-bit-line pair
02/02/2010US7656729 Circuit and method for decoding column addresses in semiconductor memory apparatus
02/02/2010US7656197 Decoder circuit
02/02/2010CA2645813C Mask programmable anti-fuse architecture
01/2010
01/28/2010US20100020629 Word line driver circuit
01/28/2010US20100020625 Electronic circuit device
01/28/2010US20100020615 Clock synchronized non-volatile memory device
01/28/2010US20100020610 Integrated Circuits Having a Controller to Control a Read Operation and Methods for Operating the Same
01/28/2010US20100020588 Semiconductor memory device
01/28/2010DE10135065B4 Halbleiterspeichervorrichtung und Verfahren für den Zugriff auf eine Speicherzelle A semiconductor memory device and method for accessing a memory cell
01/27/2010CN101636790A Decoding control with address transition detection in page erase function
01/27/2010CN101635165A Decoding circuit using low-voltage MOS transistors to realize high-voltage resistance, and realization method
01/26/2010US7653780 Semiconductor memory device and control method thereof
01/26/2010US7653687 Method for distributing content to a user station
01/26/2010US7653072 Overcoming access latency inefficiency in memories for packet switched networks
01/26/2010US7652949 Memory module and register with minimized routing path
01/26/2010US7652948 Nonvolatile memory devices and programming methods using subsets of columns
01/26/2010US7652947 Back-gate decode personalization
01/26/2010US7652946 Semiconductor device
01/26/2010US7652936 Signal sampling apparatus and method for DRAM memory
01/26/2010US7652290 Standby current erasion circuit of DRAM
01/21/2010US20100014377 Method and apparatus for reducing oscillation in synchronous circuits
01/21/2010US20100014376 Decoding circuit withstanding high voltage via low-voltage mos transistor and the implementing method thereof
01/21/2010US20100014375 Semiconductor memory device
01/21/2010US20100014371 Circuit and method for controlling a clock synchronizing circuit for low power refresh operation
01/21/2010US20100014367 Memory repair circuit and repairable pseudo-dual port static random access memory
1 ... 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 ... 194