Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 7 - Arrangements for writing information into, or reading information out from, a digital store
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
12/2001
12/25/2001US6333882 Equilibration/pre-charge circuit for a memory device
12/25/2001US6333881 Semiconductor memory
12/25/2001US6333880 Semiconductor memory device capable of detecting high-voltage test command signal
12/25/2001US6333875 Semiconductor circuit with adjustment of double data rate data latch timings
12/25/2001US6333869 Semiconductor memory device with readily changeable memory capacity
12/25/2001US6333868 Semiconductor memory device having selectively shielded data lines
12/25/2001US6333866 Semiconductor device array having dense memory cell array and heirarchical bit line scheme
12/25/2001US6333663 High voltage tolerant interface circuit
12/25/2001US6333660 Semiconductor device using complementary clock and signal input state detection circuit used for the same
12/25/2001US6333530 Semiconductor memory device having redundancy function
12/20/2001WO2001097373A2 Multiple output current mirror with improved accuracy
12/20/2001WO2001097223A2 Personal audio player with a removable multi-function module
12/20/2001US20010053195 Semiconductor device
12/20/2001US20010053107 Mask rom semiconductor memory device capable of synchronizing the activation of the sense amplfier and of the word line
12/20/2001US20010053106 Semiconductor memory device
12/20/2001US20010053105 Method and apparatus for an energy efficient operation of multiple processors in a memory
12/20/2001US20010053104 Reference signal generation for magnetic random access memory devices
12/20/2001US20010053103 Semiconductor memory with built-in cache
12/20/2001US20010053100 Delay-locked loop with binary-coupled capacitor
12/20/2001US20010053098 Semiconductor memory device having reduced current consumption at internal boosted potential
12/20/2001US20010053091 Nonvolatile memory with background operation function
12/20/2001US20010052808 Clock generation circuit generating internal clock of small variation in phase difference from external clock, and semiconductor memory device including such clock generation circuit
12/20/2001US20010052801 Sense amplifier for integrated circuits using pmos transistors
12/20/2001US20010052602 Synchronous semiconductor memory device allowing data to be satisfactorily rewritten therein
12/20/2001US20010052599 Semiconductor memory device including plurality of global data lines in parallel arrangement with low parasitic capacitance, and fabrication method thereof
12/19/2001EP1164597A2 Nonvolatile semiconductor storage device
12/19/2001EP1164595A1 Semiconductor device
12/19/2001EP1164593A1 Voltage regulator for a reference cell in a dynamic memory, reference cell, memory and method thereof
12/19/2001EP1164592A1 Dynamic random access memory and reading method thereof
12/19/2001EP1164589A1 Storage device having an error correction function
12/19/2001EP1164571A1 Driver with built-in ram, display unit with the driver, and electronic device
12/19/2001EP1164570A1 Driver with built-in ram, display unit with the driver, and electronic device
12/19/2001EP1163677A1 Integrated memory with memory cells and reference cells and corresponding operating method
12/19/2001EP1163675A1 Integrated memory with memory cells and reference cells and operating method for a memory of this type
12/19/2001CN1076547C Data radio device with changeable clock signal frequency and capable connecting with computer
12/18/2001US6331959 Semiconductor memory device and control method thereof
12/18/2001US6331958 Semiconductor memory device having data parallel/serial conversion function and capable of efficiently performing operational test
12/18/2001US6331955 Semiconductor memory device
12/18/2001US6331947 Non-volatile MOS RAM cell with capacitor-isolated nodes that are radiation accessible for rendering a non-permanent programmed information in the cell a non-volatile one
12/18/2001US6331719 Semiconductor device for reducing effects of noise on an internal circuit
12/18/2001US6330977 Electronic labeling systems and methods and electronic card systems and methods
12/13/2001WO2001095334A2 Power saving scheme for burst mode implementation during reading of data from a memory device
12/13/2001WO2001095333A1 Power saving on the fly during reading of data from a memory device
12/13/2001US20010052090 Storage device having an error correction function
12/13/2001US20010052062 Parallel computer within dynamic random access memory
12/13/2001US20010052057 Buffer for varying data access speed and system applying the same
12/13/2001US20010052046 High precision delay measurement circuit
12/13/2001US20010052045 Synchronous burst memory
12/13/2001US20010050874 Power saving scheme for burst mode implementation during reading of data from a memory device
12/13/2001US20010050873 Semiconductor memory with built-in cache
12/13/2001US20010050872 Limited swing driver circuit
12/13/2001US20010050866 Output circuit for alternating multiple bit line per column memory architecture
12/13/2001US20010050856 Semiconductor device, module including the semiconductor device, and system including the module
12/13/2001US20010050585 Digital delay line with synchronous control
12/13/2001DE10126589A1 Semiconductor memory device for providing an address access time and data access time with greater speed
12/12/2001EP1162747A2 Line segmentation in programmable logic devices having redundancy circuitry
12/12/2001EP1162624A2 Circuitry for reading from and writing to memory cells
12/12/2001EP0933785B1 Semiconductor device and power supply current detecting method
12/12/2001EP0783755B1 Initializing a read pipeline of a non-volatile sequential memory device
12/11/2001US6330638 Synchronous audio DRAM storing audio and code data
12/11/2001US6330637 Synchronous DRAM modules including multiple clock out signals for increasing processing speed
12/11/2001US6330636 Double data rate synchronous dynamic random access memory device incorporating a static RAM cache per memory bank
12/11/2001US6330202 Semiconductor memory device having write data line
12/11/2001US6330201 Semiconductor memory device exhibiting improved high speed and stable write operations
12/11/2001US6330200 Synchronous semiconductor memory device having improved operational frequency margin at data input/output
12/11/2001US6330197 System for linearizing a programmable delay circuit
12/11/2001US6330196 Circuit and method for a high data transfer rate output driver
12/11/2001US6330194 High speed I/O calibration using an input path and simplified logic
12/11/2001US6330193 Method and apparatus for low capacitance, high output impedance driver
12/11/2001US6330185 High bandwidth multi-level flash memory using dummy memory accesses to improve precision when writing or reading a data stream
12/11/2001US6330178 Ferroelectric memory device
12/11/2001US6329867 Clock input buffer with noise suppression
12/11/2001US6329240 Non-volatile memory cell and methods of fabricating and operating same
12/11/2001CA2339830C Mobile karaoke system, method used provide electromagnetic compatibility for mobile karaoke system, mobile wireless transmitting device for it, cartridge for it, method used to prevent usage of unauthorized cartridge in it and method to prevent unauthorized accessed to the data stored in it
12/06/2001WO2001093494A1 Error-correcting code adapted for memories that store multiple bits per storage cell
12/06/2001WO2001093273A2 Semiconductor memory with programmable bitline multiplexers
12/06/2001WO2001093272A2 Burst architecture for a flash memory
12/06/2001WO2001065562A8 Data balancing scheme in solid state storage devices
12/06/2001US20010049174 Method and system for configuring integrated systems on a chip
12/06/2001US20010048634 Synchronous semiconductor memory device
12/06/2001US20010048633 Semiconductor memory circuit including a data output circuit
12/06/2001US20010048628 Method of controlling line memory
12/06/2001US20010048625 Dynamically configurated storage array with improved data access
12/06/2001US20010048620 Layout of a sense amplifier with accelerated signal evaluation
12/06/2001US20010048617 Semiconductor integrated circuit
12/06/2001US20010048610 Semiconductor memory device
12/06/2001DE3943808C2 Direct access memory with distributed memory banks
12/06/2001DE10122703A1 Charakterisierung von Leseverstärkern Characterization of sense amplifiers
12/04/2001US6327667 Apparatus and method for operating clock sensitive devices in multiple timing domains
12/04/2001US6327633 Solid state audio system
12/04/2001US6327217 Variable latency buffer circuits, latency determination circuits and methods of operation thereof
12/04/2001US6327216 Full page increment/decrement burst for DDR SDRAM/SGRAM
12/04/2001US6327215 Local bit switch decode circuit and method
12/04/2001US6327214 Multi-bank memory device having input and output amplifier shared by adjacent memory banks
12/04/2001US6327213 Semiconductor integrated circuit device having a hierarchical power source configuration
12/04/2001US6327207 Synchronizing data operations across a synchronization boundary between different clock domains using two-hot encoding
12/04/2001US6327206 Semiconductor memory device including serial/parallel conversion circuit
12/04/2001US6327204 Method of storing information in a memory cell
12/04/2001US6327203 Memory device having minimized power consumption and data read and write method of the same
12/04/2001US6327202 Bit line pre-charge in a memory
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