| Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197) |
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| 04/15/2003 | US6549446 Data balancing scheme in solid state storage devices |
| 04/15/2003 | US6549445 Semiconductor memory device including plurality of global data lines in parallel arrangement with low parasitic capacitance, and fabrication method thereof |
| 04/15/2003 | US6549444 Memory device with prefetched data ordering distributed in prefetched data path logic, circuit, and method of ordering prefetched data |
| 04/15/2003 | US6549417 Information processing apparatus |
| 04/10/2003 | WO2003030176A2 Memory array employing integral isolation transistors |
| 04/10/2003 | WO2003029984A1 Apparatus and methods for dedicated command port in memory controllers |
| 04/10/2003 | WO2003029951A2 Non-volatile memory control |
| 04/10/2003 | US20030070064 Circuit and method capable of adjusting the external clock of a CPU |
| 04/10/2003 | US20030070037 Memory device command signal generator |
| 04/10/2003 | US20030067835 Memory device |
| 04/10/2003 | US20030067834 Switching circuit capable of improving memory write timing and method thereof |
| 04/10/2003 | US20030067833 Bit line selection circuit having hierarchical structure |
| 04/10/2003 | US20030067830 Method and apparatus for temperature adaptive refresh in 1T-SRAM compatible memory using the subthreshold characteristics of MOSFET transistors |
| 04/10/2003 | US20030067823 Memory read circuitry |
| 04/10/2003 | US20030067821 Digital memory circuit having a plurality of memory areas |
| 04/10/2003 | US20030067820 Digital memory circuit having a plurality of segmented memory areas |
| 04/10/2003 | US20030067817 Distributed write data drivers for burst access memories |
| 04/10/2003 | US20030067812 Clock synchronous semiconductor memory device |
| 04/10/2003 | US20030067799 Adjustable memory self-timing circuit |
| 04/10/2003 | US20030067338 Digitally controllable internal clock generating circuit of semiconductor memory device and method for same |
| 04/10/2003 | US20030067334 Circuit configuration for processing data, and method for identifying an operating state |
| 04/10/2003 | US20030067332 Method and circuit for adjusting the timing of output data based on an operational mode of output drivers |
| 04/10/2003 | US20030067330 Method and circuit for adjusting the timing of ouput data based on an operational mode of output drivers |
| 04/10/2003 | US20030067328 Differential input buffer with auxiliary bias pulser circuit |
| 04/10/2003 | US20030067081 Digit line architecture for dynamic memory |
| 04/10/2003 | US20030067063 Semiconductor module having a configurable data width of an output bus, and a housing configuration having a semiconductor module |
| 04/10/2003 | US20030067043 Three-dimensional memory |
| 04/10/2003 | US20030067018 System with meshed power and signal buses on cell array |
| 04/09/2003 | EP1299885A1 Addressing of memory matrix |
| 04/09/2003 | CN1409860A Plateline sensing |
| 04/09/2003 | CN1409492A Error-correcting code circuit |
| 04/09/2003 | CN1409398A Strong dielectric memory device and its producing method |
| 04/09/2003 | CN1409226A Controller for sectional access control |
| 04/09/2003 | CN1105419C Interleaved and sequential counter |
| 04/09/2003 | CN1105389C Memory suitable for operation at low power supply voltage and reading amplifier thereof |
| 04/09/2003 | CN1105358C Semiconductor memory having arithmetic function, and processor using same |
| 04/08/2003 | US6546476 Read/write timing for maximum utilization of bi-directional read/write bus |
| 04/08/2003 | US6546461 Multi-port cache memory devices and FIFO memory devices having multi-port cache memory devices therein |
| 04/08/2003 | US6546460 Recording and/or reproducing method and apparatus |
| 04/08/2003 | US6546446 Synchronous memory device having automatic precharge |
| 04/08/2003 | US6545942 Semiconductor memory device and information processing unit |
| 04/08/2003 | US6545941 Clock synchronous circuit |
| 04/08/2003 | US6545940 Semiconductor integrated circuit having enhanced acquisition of external signal |
| 04/08/2003 | US6545938 Buffering circuit in a semiconductor memory device |
| 04/08/2003 | US6545937 Write circuit of a memory device |
| 04/08/2003 | US6545936 Pipeline structure of memory for high-fast row-cycle |
| 04/08/2003 | US6545934 Semiconductor memory device having configuration suited for high integration |
| 04/08/2003 | US6545933 Semiconductor memory |
| 04/08/2003 | US6545932 SDRAM and method for data accesses of SDRAM |
| 04/08/2003 | US6545927 Integrated semiconductor circuit, in particular a semiconductor memory configuration, and method for its operation |
| 04/08/2003 | US6545925 Semiconductor device with self refresh test mode |
| 04/08/2003 | US6545922 Semiconductor memory device |
| 04/08/2003 | US6545919 Semiconductor memory and output signal control method and circuit in semiconductor memory |
| 04/08/2003 | US6545909 Nonvolatile semiconductor memory device |
| 04/08/2003 | US6545901 Semiconductor memory device having a supplemental element for reading data stored in a memory element |
| 04/08/2003 | US6545899 ROM embedded DRAM with bias sensing |
| 04/08/2003 | US6545898 Method and apparatus for writing memory arrays using external source of high programming voltage |
| 04/08/2003 | US6545897 Dynamic RAM-and semiconductor device |
| 04/08/2003 | US6545528 Semiconductor device |
| 04/03/2003 | WO2003028035A1 Multiple discharge capable bit line |
| 04/03/2003 | WO2003028033A2 Segmented metal bitlines |
| 04/03/2003 | WO2002073658A3 Yield and speed enhancement of semiconductor integrated circuits using post-fabrication transistor mismatch compensation circuitry |
| 04/03/2003 | US20030065900 Semiconductor memory asynchronous pipeline |
| 04/03/2003 | US20030065838 Method and system for attaching multiple clock sources to an SDRAM memory array |
| 04/03/2003 | US20030065465 Method and apparatus providing improved data path calibration for memory devices |
| 04/03/2003 | US20030063519 Semiconductor integrated circuit device |
| 04/03/2003 | US20030063514 Integrated data input sorting and timing circuit for double data rate (DDR) dynamic random access memory (DRAM) devices |
| 04/03/2003 | US20030063512 Semiconductor storage device |
| 04/03/2003 | US20030063511 Leakage-tolerant memory arrangements |
| 04/03/2003 | US20030063507 Methods and apparatus for reading memory device register data |
| 04/03/2003 | US20030063506 Integrated memory device, method of operating an integrated memory, and memory system having a plurality of integrated memories |
| 04/03/2003 | US20030063505 Dram |
| 04/03/2003 | US20030063502 Distributed write data drivers for burst access memories |
| 04/03/2003 | US20030063496 Memory sense amplifier |
| 04/03/2003 | US20030063493 Semiconductor memory device improving operation margin and increasing operation speed regardless of variations in semiconductor manufacturing processes |
| 04/03/2003 | US20030063489 Semiconductor device with high speed latch operation |
| 04/03/2003 | US20030062942 Input circuit and semiconductor integrated circuit having the input circuit |
| 04/03/2003 | US20030062905 Circuit configuration and method for assessing capacitances in matrices |
| 04/03/2003 | US20030062556 Memory array employing integral isolation transistors |
| 04/03/2003 | US20030062547 Semiconductor memory device |
| 04/02/2003 | EP1298730A2 Ferroelectric memory and method for fabricating the same |
| 04/02/2003 | EP1298668A2 Semiconductor memory device including clock-independent sense amplifier |
| 04/02/2003 | EP1298667A2 Semiconductor memory device |
| 04/02/2003 | EP1297535A1 Reference cell for high speed sensing in non-volatile memories |
| 04/02/2003 | EP1297529A2 Block-level read while write method and apparatus |
| 04/02/2003 | CN1407627A Non-volatility memory unit with separate bit line structure |
| 04/02/2003 | CN1407558A 半导体存储器 Semiconductor memory |
| 04/02/2003 | CN1104728C Memory circuit and data control circuit of memory circuit and address assigning circuit of memory circuit |
| 04/02/2003 | CN1104727C Storage device with layered position-line |
| 04/02/2003 | CN1104695C 半导体集成电路 The semiconductor integrated circuit |
| 04/01/2003 | US6543027 On-chip detection of clock gitches by examination of consecutive data |
| 04/01/2003 | US6543017 Semiconductor storage device |
| 04/01/2003 | US6542976 Memory device having an internal register |
| 04/01/2003 | US6542959 Memory refreshing system |
| 04/01/2003 | US6542957 Memory of controlling page mode access |
| 04/01/2003 | US6542569 Memory device command buffer apparatus and method and memory devices and computer systems using same |
| 04/01/2003 | US6542445 Method for editing a playlist to read main data in a desired reproduction sequence |
| 04/01/2003 | US6542430 Integrated memory and memory configuration with a plurality of memories and method of operating such a memory configuration |
| 04/01/2003 | US6542429 Method of controlling line memory |
| 04/01/2003 | US6542428 Semiconductor memory device allowing increase in capacity and operation speed with a suppressed layout area |