| Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197) |
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| 04/29/2003 | US6556502 Memory circuitry for programmable logic integrated circuit devices |
| 04/29/2003 | US6556497 Refresh controller and address remapping circuit and method for dual mode full/reduced density DRAMs |
| 04/29/2003 | US6556494 High frequency range four bit prefetch output data path |
| 04/29/2003 | US6556489 Method and apparatus for determining digital delay line entry point |
| 04/29/2003 | US6556488 Delay locked loop for use in semiconductor memory device |
| 04/29/2003 | US6556486 Circuit configuration and method for synchronization |
| 04/29/2003 | US6556485 Output buffer capable of adjusting current drivability and semiconductor integrated circuit device having the same |
| 04/29/2003 | US6556484 Plural line buffer type memory LSI |
| 04/29/2003 | US6556483 Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths |
| 04/29/2003 | US6556482 Semiconductor memory device |
| 04/29/2003 | US6556472 Static RAM with optimized timing of driving control signal for sense amplifier |
| 04/29/2003 | US6556068 Threshold voltage compensation circuits for low voltage and low power CMOS integrated circuits |
| 04/29/2003 | US6556052 Semiconductor controller device having a controlled output driver characteristic |
| 04/29/2003 | US6556051 Apparatus for providing both supports including synchronous dynamic random access memory (SDRAM) module and double data rate (DDR) DRAM module |
| 04/29/2003 | US6556045 Digital designs optimized with time division multiple access technology |
| 04/24/2003 | WO2002101747A3 Draw with bit line precharging, inverting data writing, retained data output and reduced power consumption |
| 04/24/2003 | US20030079111 Device for linking a processor to a memory element and memory element |
| 04/24/2003 | US20030079097 Optical navigation sensor with shadow memory |
| 04/24/2003 | US20030079095 Triggering of IO equilibrating ending signal with firing of column access signal |
| 04/24/2003 | US20030076733 Synchronous flash memory command sequence |
| 04/24/2003 | US20030076730 Nonvolatile semiconductor memory device of dual-operation type with data protection function |
| 04/24/2003 | US20030076720 First bit databurst firing of IO equilibrating ending signal based on column access signal |
| 04/24/2003 | US20030076717 Non-volatile semiconductor memory apparatus |
| 04/24/2003 | US20030076714 Semiconductor integrated circuit, and a data storing method thereof |
| 04/24/2003 | US20030076712 Memory device and process for improving the state of a termination |
| 04/24/2003 | US20030076702 Semiconductor memory device having first and second memory architecture and memory system using the same |
| 04/24/2003 | US20030076295 Input device and input and output device |
| 04/24/2003 | US20030076143 Semiconductor device, semiconductor system, and digital delay circuit |
| 04/23/2003 | EP1304617A2 Optical navigation sensor with shadow memory |
| 04/23/2003 | EP1303877A2 Semiconductor memory architecture |
| 04/23/2003 | EP1125300B1 Method and apparatus for increasing the time available for refresh for 1-t sram compatible devices |
| 04/23/2003 | CN1412849A Semiconductor |
| 04/23/2003 | CN1412777A High density memory read amplifier |
| 04/23/2003 | CN1412776A Circuit for raising sensing amplifier speed and its stability and its method |
| 04/22/2003 | US6553451 Memory command converter and application system |
| 04/22/2003 | US6552976 Storage and reproduction apparatus |
| 04/22/2003 | US6552960 Semiconductor integrated circuit device |
| 04/22/2003 | US6552959 Semiconductor memory device operable for both of CAS latencies of one and more than one |
| 04/22/2003 | US6552957 Semiconductor integrated circuit having a signal receiving circuit |
| 04/22/2003 | US6552956 Semiconductor memory device and non-volatile semiconductor memory device provided with a plurality of internal counters |
| 04/22/2003 | US6552955 Semiconductor memory device with reduced power consumption |
| 04/22/2003 | US6552954 Semiconductor integrated circuit device |
| 04/22/2003 | US6552953 High speed signal path and method |
| 04/22/2003 | US6552952 Column multiplexer for semiconductor memories |
| 04/22/2003 | US6552949 Reducing leakage current in a memory device |
| 04/22/2003 | US6552948 Methods and systems for reducing heat flux in memory systems |
| 04/22/2003 | US6552945 Method for storing a temperature threshold in an integrated circuit, method for storing a temperature threshold in a dynamic random access memory, method of modifying dynamic random access memory operation in response to temperature, programmable temperature sensing circuit and memory integrated circuit |
| 04/22/2003 | US6552944 Single bitline direct sensing architecture for high speed memory device |
| 04/22/2003 | US6552943 Sense amplifier for dynamic random access memory (“DRAM”) devices having enhanced read and write speed |
| 04/22/2003 | US6552942 Data line precharging circuit of a semiconductor memory device |
| 04/22/2003 | US6552936 Semiconductor storage apparatus |
| 04/22/2003 | US6552932 Segmented metal bitlines |
| 04/22/2003 | US6552930 Semiconductor memory device and storage method thereof |
| 04/22/2003 | US6552587 Synchronous semiconductor device for adjusting phase offset in a delay locked loop |
| 04/22/2003 | US6552357 Semiconductor memory device having plate lines and precharge circuits |
| 04/22/2003 | US6552044 Indane or dihydroindole derivatives |
| 04/22/2003 | US6551852 Method of forming a recessed magnetic storage element |
| 04/22/2003 | CA2294164C Optical logic element and methods for respectively its preparation and optical addressing, as well as the use thereof in an optical logic device |
| 04/17/2003 | WO2003032372A1 A three-dimensional memory |
| 04/17/2003 | WO2003032322A2 Adjustable memory self-timing circuit |
| 04/17/2003 | WO2003032160A2 Circuit architecture protected against perturbations |
| 04/17/2003 | WO2003005367A3 tMART MEMORY |
| 04/17/2003 | WO2002033706A3 Noise suppression for open bit line dram architectures |
| 04/17/2003 | US20030074630 Method for combining refresh operation with parity validation in a DRAM-based content addressable memory (CAM) |
| 04/17/2003 | US20030074517 Control means for burst access control |
| 04/17/2003 | US20030072205 Bitline precharge |
| 04/17/2003 | US20030072201 Semiconductor memory device having bit line kicker |
| 04/17/2003 | US20030072199 Semiconductor memory device |
| 04/17/2003 | US20030072194 Nonvolatile semiconductor storage device |
| 04/17/2003 | US20030072193 Nonvolatile semiconductor storage device |
| 04/17/2003 | US20030072191 Non-volatile semiconductor memory device |
| 04/17/2003 | US20030072189 Semiconductor device preventing signal delay among wirings |
| 04/17/2003 | US20030072188 Control circuitry for a non-volatile memory |
| 04/17/2003 | US20030072187 Semiconductor storage device conducting a late-write operation and controlling a test read-operation to read data not from a data latch circuit but from a memory core circuit regardless of whether a preceding address and a present address match each other |
| 04/17/2003 | US20030072183 High speed memory array architecture |
| 04/17/2003 | US20030072172 Noise suppression for open bit line DRAM architectures |
| 04/17/2003 | DE10161347C1 Clock signal conversion circuit used with phase-locked loop circuit has 2 difference amplifiers each converting input clock signal pair into unsymmetrical clock signals |
| 04/16/2003 | EP1302948A1 Memory sense amplifier |
| 04/16/2003 | EP1301927A1 Method and apparatus for synchronization of row and column access operations |
| 04/16/2003 | EP1031203A4 Delay locked loop circuitry for clock delay adjustment |
| 04/16/2003 | EP0972270B1 A storage apparatus and writing and/or reading methods for use in hierarchical coding |
| 04/16/2003 | CN1411601A Mobile communication device having integrated embedded flash and SRAM memory |
| 04/16/2003 | CN1411073A Semiconductor storage |
| 04/16/2003 | CN1411070A Semiconductor storage |
| 04/16/2003 | CN1411069A 半导体装置 Semiconductor device |
| 04/16/2003 | CN1411064A 半导体集成电路装置 The semiconductor integrated circuit device |
| 04/16/2003 | CN1106019C 半导体存储器 Semiconductor memory |
| 04/15/2003 | US6549994 Semiconductor memory device capable of performing a write operation 1 or 2 cycles after receiving a write command without a dead cycle |
| 04/15/2003 | US6549975 Tri-stating output buffer during initialization of synchronous memory |
| 04/15/2003 | US6549485 Control and timing structure for a memory |
| 04/15/2003 | US6549484 Semiconductor device |
| 04/15/2003 | US6549483 RAM having dynamically switchable access modes |
| 04/15/2003 | US6549481 Power up initialization circuit responding to an input signal |
| 04/15/2003 | US6549476 Device and method for using complementary bits in a memory array |
| 04/15/2003 | US6549475 Semiconductor memory device and information device |
| 04/15/2003 | US6549472 Packet-based integrated circuit dynamic random access memory device incorporating an on-chip row register cache to reduce data access latencies |
| 04/15/2003 | US6549471 Adiabatic differential driver |
| 04/15/2003 | US6549470 Small signal, low power read data bus driver for integrated circuit devices incorporating memory arrays |
| 04/15/2003 | US6549464 Nonvolatile semiconductor memory device |
| 04/15/2003 | US6549449 Semiconductor device |