Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 7 - Arrangements for writing information into, or reading information out from, a digital store
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
09/2003
09/09/2003US6617629 Optically readable ferroelectric memory cell
09/04/2003WO2003073290A1 Pipelined parallel programming operation in a non-volatile memory system
09/04/2003WO2003073259A1 Direct memory swapping between nand flash and sram with error correction coding
09/04/2003WO2003072370A1 Device, system and method for data exchange
09/04/2003WO2002039231A9 Media storage device management
09/04/2003US20030167417 Method and apparatus for capturing data from a memory subsystem
09/04/2003US20030167374 Double data rate synchronous sram with 100% bus utilization
09/04/2003US20030164510 Redundancy architecture for repairing semiconductor memories
09/04/2003CA2476913A1 Direct memory swapping between nand flash and sram with error correction coding
09/03/2003EP1341181A2 Semiconductor devices, circuits and mehtods for synchronizing the inputting and outputting data by internal clock signals derived from single feedback loop
09/03/2003EP1341172A2 Memory sharing techniques in compressed audio stream data decoder
09/03/2003CN2570877Y Recrudescer capable of making interfering signals
09/03/2003CN2570875Y MP3 digital visible recrudescer
09/03/2003CN1440555A Block level read while write method and apparatus
09/03/2003CN1440553A Addressing of memory matrix
09/03/2003CN1120496C Apparatus and method for simplified analog signal record and playback
09/03/2003CN1120495C High performance universal multi-port internally cached dynamic randon access memory system, architecture and method
09/02/2003US6615325 Method for switching between modes of operation
09/02/2003US6615309 Semiconductor memory device
09/02/2003US6615307 Flash with consistent latency for read operations
09/02/2003US6615294 Recording/reproducing apparatus using an IC memory
09/02/2003US6614715 Integrated circuit memory device having interleaved read and program capabilities and methods of operating same
09/02/2003US6614714 Semiconductor memory system having a data clock system for reliable high-speed data transfers
09/02/2003US6614710 Semiconductor memory device and data read method thereof
09/02/2003US6614709 Method and apparatus for processing commands in a queue coupled to a system or memory
09/02/2003US6614703 Method and system for configuring integrated systems on a chip
09/02/2003US6614702 Semiconductor memory devices and methods including coupling and/or floating isolation control signal lines
09/02/2003US6614700 Circuit configuration with a memory array
09/02/2003US6614698 Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths
09/02/2003US6614696 Semiconductor device having memory cells coupled to read and write data lines
09/02/2003US6614679 Semiconductor memory device
09/02/2003US6614268 High-speed, low-power inter-chip transmission system
09/02/2003US6614266 Semiconductor integrated circuit
09/02/2003US6613661 Process for fabricating secure integrated circuit
08/2003
08/28/2003WO2003071550A1 Semiconductor integrated circuit device
08/28/2003WO2003071436A1 External connection device, host device, and data communication system
08/28/2003WO2003044803A3 Sense amplifier for multilevel non-volatile integrated memory devices
08/28/2003WO2002046873A3 System and method for managing information objects
08/28/2003US20030163636 Circuit for implementing special mode in packet-based semiconductor memory device
08/28/2003US20030163629 Pipelined parallel programming operation in a non-volatile memory system
08/28/2003US20030163622 Device, system and method for data exchange
08/28/2003US20030163606 High-speed memory system
08/28/2003US20030163328 Method and system for allocating memory during encoding of a datastream
08/28/2003US20030163327 Compressed audio stream data decoder memory sharing techniques
08/28/2003US20030161250 Memory device having reduced layout area
08/28/2003US20030161210 Control circuit for an S-DRAM
08/28/2003US20030161207 Look-ahead refresh for an integrated circuit memory
08/28/2003US20030161206 Circuit and method for reducing memory idle cycles
08/28/2003US20030161203 Multi-level semiconductor memory architecture and method of forming the same
08/28/2003US20030161196 High-speed memory system
08/28/2003US20030161194 Matchline sense circuit and method
08/28/2003US20030161193 Data storage and exchange device
08/28/2003US20030161189 Precharge method and precharge voltage gerneration circuit of signal line
08/28/2003US20030161188 Nonvolatile semiconductor memory device programming second dynamic reference cell according to threshold value of first dynamic reference cell
08/28/2003US20030160645 Semiconductor integrated circuit including command decoder for receiving control signals
08/28/2003US20030160289 Data input circuit for reducing loading difference between fetch signal and multiple data in semiconductor device
08/27/2003EP1339070A1 Readout method of a memory cell content for data storage
08/27/2003EP1339064A2 Semiconductor memory device
08/27/2003EP1338013A2 Circuit arrangement
08/27/2003CN1439160A Matchline sense circuit and method
08/27/2003CN1438649A Non-volatile semiconductor storage device and data read-out method
08/27/2003CN1119816C Synchronous semiconductor storage device having timed circuit of controlling activation/non-activation of word line
08/27/2003CN1119814C Semiconductor stroage devie
08/26/2003US6611885 Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths
08/26/2003US6611475 System and method for skew compensating a clock signal and for capturing a digital signal using the skew compensated clock signal
08/26/2003US6611473 Power-saving modes for memories
08/26/2003US6611465 Diffusion replica delay circuit
08/26/2003US6611464 Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics
08/26/2003US6611462 Semiconductor integrated circuit
08/26/2003US6611456 Method and apparatus for reducing the number of programmed bits in a memory array
08/26/2003US6611454 Thin film magnetic memory device writing data of a plurality of bits in parallel
08/26/2003US6611452 Reference cells for TCCT based memory cells
08/26/2003US6611446 Semiconductor memory with multistage local sense amplifier
08/26/2003US6611217 Initialization system for recovering bits and group of bits from a communications channel
08/21/2003WO2003069486A1 A memory and an adaptive timing system for controlling access to the memory
08/21/2003WO2003069484A2 Method and apparatus for supplementary command bus in a computer system
08/21/2003WO2003069461A2 Methods and apparatus for adaptively adjusting a data receiver
08/21/2003US20030159092 Hot swapping memory method and system
08/21/2003US20030156488 Synchronous DRAM controller
08/21/2003US20030156486 Semiconductor memory device capable of reading at high speed
08/21/2003US20030156484 Fast accessing of a memory device
08/21/2003US20030156481 Semiconductor memory device and control method
08/21/2003US20030156480 Control module comprising a ROM with reduced electrical consumption
08/21/2003US20030156478 Nonvolatile semiconductor memory device and data readout method for the same
08/21/2003US20030156473 Memory controller
08/21/2003US20030156472 Semiconductor integrated circuit device
08/21/2003US20030156466 Physically alternating sense amplifier activation
08/21/2003US20030156465 System and method for multiplexing data and data masking information on a data bus of a memory device
08/21/2003US20030156464 Semiconductor memory device operating in synchronization with clock signal
08/21/2003US20030156462 Memory devices having power supply routing for delay locked loops that counteracts power noise effects
08/21/2003US20030156461 Method and apparatus for simultaneous differential data sensing and capture in a high speed memory
08/21/2003US20030156459 Nonvolatile memory system, semiconductor memory, and writing method
08/21/2003US20030156458 Sense amplifier structure for multilevel non-volatile memory devices and corresponding reading method
08/21/2003US20030156455 Semiconductor integrated circuit adapted to output pass/fail results of internal operations
08/21/2003US20030156454 Direct memory swapping between NAND flash and SRAM with error correction coding
08/21/2003US20030156453 Integrated memory and method for operating an integrated memory
08/21/2003US20030155948 High-speed sense amplifier with auto-shutdown precharge path
08/20/2003EP1336972A1 Method and apparatus for data inversion in a memory device
08/20/2003EP1336971A1 Storage module
08/20/2003EP0960536B1 Queuing structure and method for prioritization of frames in a network switch
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