Patents
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
07/2003
07/22/2003US6597225 Data capture circuit with series channel sampling structure
07/22/2003US6596626 Method for arranging wiring line including power reinforcing line and semiconductor device having power reinforcing line
07/17/2003WO2003058636A1 Active leakage control in single-ended full-swing caches
07/17/2003WO2003058635A1 Increasing a refresh period in a semiconductor memory device
07/17/2003WO2003058630A1 Multi-mode synchronous memory device and method of operating and testing same
07/17/2003WO2003012795A3 Fuse programmable i/o organization
07/17/2003US20030135776 Method and arrangement for correcting data
07/17/2003US20030135707 Semiconductor memory device with fast masking process in burst write mode
07/17/2003US20030135699 Multi-port memory based on DRAM core
07/17/2003US20030135698 Method and apparatus for multi-path data storage and retrieval
07/17/2003US20030135697 Integrated circuit memory device supporting an N bit prefetch scheme and a 2N burst length
07/17/2003US20030135690 Nand flash memory device
07/17/2003US20030135515 Tuple space operations for fine grained system control
07/17/2003US20030133527 Method and circuit for adjusting the timing of output data based on the current and future states of the output data
07/17/2003US20030133352 Read compression in a memory
07/17/2003US20030133351 Semiconductor memory device allowing increase in capacity and operation speed with a suppressed layout area
07/17/2003US20030133347 Wide databus architecture
07/17/2003US20030133346 Semiconductor memory device
07/17/2003US20030133345 Synchronous mirror delay with reduced delay line taps
07/17/2003US20030133339 Interconnected high speed electron tunneling devices
07/17/2003US20030133338 Semiconductor device, nonvolatile semiconductor memory, system including a plurality of semiconductor devices or nonvolatile semiconductor memories, electric card including semiconductor device or nonvolatile semiconductor memory, and electric device with which this electric card can be used
07/17/2003US20030133332 Semiconductor memory device having write column select line or read column select line for shielding signal line
07/17/2003US20030133331 Cas latency select utilizing multilevel signaling
07/17/2003US20030133328 Current sense amplifier with dynamic pre-charge
07/17/2003US20030133321 Random access memory and method for controlling operations of reading, writing, and refreshing data of the same
07/17/2003US20030133320 Twisted bit-line compensation
07/17/2003US20030132478 Multi-state operation of dual floating gate array
07/17/2003US20030132457 Scalable hierarchical I/O line structure for a semiconductor memory device
07/16/2003EP1327991A2 Apparatus and method for pipelined memory operations
07/16/2003EP1327990A2 Semiconductor memory device
07/16/2003EP1327988A1 Retrieval method and an apparatus for a multimedia database
07/16/2003EP1327248A2 Methods and systems for reducing heat flux in memory systems
07/16/2003EP1019911B1 Apparatus and method for device timing compensation
07/16/2003EP0741902B1 Improved memory devices
07/16/2003CN1430783A Semiconductor memory and controlling method thereof
07/16/2003CN1430151A Main memory based on rapid memory
07/16/2003CN1114993C Signal state transition detector circuit
07/16/2003CN1114950C Semiconductor device
07/16/2003CN1114926C Semiconductor memory device
07/15/2003US6594197 Semiconductor integrated circuit device
07/15/2003US6594196 Multi-port memory device and system for addressing the multi-port memory device
07/15/2003US6594190 Semiconductor device with output latch circuit outputting complementary data at high speed
07/15/2003US6594188 Integrated memory having a cell array and charge equalization devices, and method for the accelerated writing of a datum to the integrated memory
07/15/2003US6594187 Semiconductor memory
07/15/2003US6594173 Method for digit line architecture for dynamic memory
07/15/2003US6594171 Memory systems and methods of making the same
07/15/2003US6594170 Semiconductor integrated circuit device and semiconductor device system
07/15/2003US6594169 Semiconductor memory device and memory system
07/15/2003US6593613 Memory cell for plateline sensing
07/10/2003WO2003056433A1 Memory device and recording/reproducing apparatus using the same
07/10/2003WO2003056432A1 Memory device and recording/reproducing apparatus using the same
07/10/2003WO2003056431A1 Memory device and recording/reproducing apparatus using the same
07/10/2003WO2003038567A3 Digital audio device
07/10/2003WO2002101746A3 Sense amplifier with improved latching
07/10/2003WO2002025448A3 Adaptive throttling of memory accesses, such as throttling rdram accesses in a real-time system
07/10/2003US20030131307 System and method of recovering from soft memory errors
07/10/2003US20030131210 Method and arrangement for the verification of NV fuses as well as a corresponding computer program product and a corresponding computer-readable storage medium
07/10/2003US20030131161 Device and method for maximizing performance on a memory interface with a variable number of channels
07/10/2003US20030131160 Timing calibration apparatus and method for a memory device signaling system
07/10/2003US20030128622 Synchronous mirror delay with reduced delay line taps
07/10/2003US20030128621 Auto-disable receive control for ddr receive strobes
07/10/2003US20030128611 Multiple mode elastic data transfer interface
07/10/2003US20030128610 ROM embedded DRAM with bias sensing
07/10/2003US20030128609 DRAM with bias sensing
07/10/2003US20030128608 Sense amplifier driver circuits configured to track changes in memory cell pass transistor characteristics
07/10/2003US20030128607 Semiconductor memory device and electronic instrument using the same
07/10/2003US20030128599 Active termination circuit and method for controlling the impedance of external integrated circuit terminals
07/10/2003US20030128598 Semiconductor memory device including a delaying circuit capable of generating a delayed signal with a substantially constant delay time
07/10/2003US20030128597 Semiconductor devices, circuits and methods for synchronizing the inputting and outputting data by internal clock signals derived from single feedback loop
07/10/2003US20030128596 Method and apparatus for generating multiple system memory drive strengths
07/10/2003US20030128593 Semiconductor storage apparatus
07/10/2003US20030128592 Semiconductor circuit configuration
07/10/2003US20030128589 Method and architecture to calibrate read operations in synchronous flash memory
07/10/2003US20030128585 Semiconductor memory device having faulty cells
07/10/2003US20030128573 Semiconductor memory system having dynamically delayed timing for high-speed data transfers
07/10/2003US20030128567 Sensing apparatus for a ROM memory device
07/10/2003US20030128566 ROM embedded DRAM with bias sensing
07/10/2003US20030128065 Circuit assembly for converting a differential input clock signal pair into a single-ended output clock signal
07/10/2003US20030128055 Low power latch sense amplifier
07/09/2003EP1326258A2 Single supply voltage, nonvolatile phase change memory device with cascoded column selection and simultaneous word read/write operations
07/09/2003EP1326257A2 Pipelined programming for a NAND type flash memory
07/09/2003EP1326255A2 Non-volatile storage latch
07/09/2003EP1326253A2 Nonvolatile storage device and operating method thereof
07/09/2003EP1326251A2 Computer memory
07/09/2003CN1428866A 半导体集成电路 The semiconductor integrated circuit
07/09/2003CN1428789A Data access method of semiconductor memory and semiconductor memory
07/09/2003CN1428784A Semiconductor memory with read amplifier
07/08/2003US6591353 Protocol for communication with dynamic memory
07/08/2003US6591328 Non-volatile memory storing address control table data formed of logical addresses and physical addresses
07/08/2003US6590827 Clock device for supporting multiplicity of memory module types
07/08/2003US6590824 Dynamic semiconductor memory with refresh and method for operating such a memory
07/08/2003US6590822 System and method for performing partial array self-refresh operation in a semiconductor memory device
07/08/2003US6590821 Memory device
07/08/2003US6590820 Sense amplifier with reference cell circuit
07/08/2003US6590819 Digit line equilibration using time-multiplexed isolation
07/08/2003US6590804 Adjustable current mode differential amplifier
07/08/2003US6590796 Semiconductor memory device with variably set data input-output terminals and control signal terminals for the same
07/08/2003US6590434 Delay time controlling circuit and method for controlling delay time
07/08/2003US6590429 Data receivers for reproducing data input signals and methods for detecting data signals in data input receivers
07/08/2003US6590428 Evaluation of conduction at precharged node