Patents
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
08/2003
08/05/2003US6603706 Method and apparatus for synchronization of read data in a read data synchronization circuit
08/05/2003US6603705 Method of allowing random access to rambus DRAM for short burst of data
08/05/2003US6603695 Semiconductor memory device having self-refresh mode
08/05/2003US6603693 DRAM with bias sensing
08/05/2003US6603688 Semiconductor memory device having improved arrangement for replacing failed bit lines
08/05/2003US6603687 Semiconductor devices, circuits and methods for synchronizing the inputting and outputting data by internal clock signals derived from single feedback loop
08/05/2003US6603686 Semiconductor memory device having different data rates in read operation and write operation
08/05/2003US6603684 Semiconductor memory device having noise tolerant input buffer
08/05/2003US6603683 Decoding scheme for a stacked bank architecture
08/05/2003US6603170 Integrated semiconductor configuration having a semiconductor memory with user programmable bit width
07/2003
07/31/2003WO2003063250A1 Programmable memory address and decode circuits with ultra thin vertical body transistors
07/31/2003WO2003063173A1 Mram without isolation devices
07/31/2003WO2003046925A3 Built-in self-testing for double data rate input/output interface
07/31/2003US20030145188 Look ahead methods and apparatus
07/31/2003US20030145184 DRAM having SRAM equivalent interface
07/31/2003US20030145177 Computer readable storage medium and semiconductor integrated circuit device
07/31/2003US20030145176 Mass storage device architecture and operation
07/31/2003US20030145161 Apparatus and method to track command signal occurrence for dram data transfer
07/31/2003US20030145158 Embedded DRAM system having wide data bandwidth and data transfer data protocol
07/31/2003US20030145156 Apparatus and method to track flag transitions for DRAM data transfer
07/31/2003US20030145153 Non volatile memory device with multiple ports
07/31/2003US20030142724 Integrated circuit with temperature sensor and method for heating the circuit
07/31/2003US20030142577 Synchronous semiconductor memory device with a plurality of memory banks and method of controlling the same
07/31/2003US20030142576 Semiconductor integrated circuit device
07/31/2003US20030142570 Memory controller and serial memory
07/31/2003US20030142569 Capacitive techniques to reduce noise in high speed interconnections
07/31/2003US20030142568 Circuit for controlling a reference node in a sense amplifier
07/31/2003US20030142567 Method and apparatus for accelerating signal equalization between a pair of signal lines
07/31/2003US20030142558 Embedded DRAM system having wide data bandwidth and data transfer data protocol
07/31/2003US20030142557 Apparatus and method for encoding auto-precharge
07/31/2003US20030142545 Non-volatile semiconductor memory device
07/31/2003US20030142534 Semiconductor device
07/31/2003US20030142526 Semiconductor integrated circuit device
07/31/2003US20030141897 Multi-access FIFO queue
07/31/2003US20030141896 Method and apparatus for low capacitance, high output impedance driver
07/30/2003EP1330828A2 Upscaled clock feeds memory to make parallel waves
07/30/2003CN1433028A Semiconductor device, circuit and method with synchronous input and output data
07/30/2003CN1433027A Drive capacity setting method and program and its driver circuit
07/30/2003CN1433026A Semiconductor memroy containing delay circuit capable of generating sufficiently stable delay signal
07/30/2003CN1433025A AC timing parameter controlling circuit and method for semiconductor memory equipment
07/30/2003CN1433019A Method of writing data bits into memory array
07/30/2003CN1432920A NAND flash memory
07/30/2003CN1116683C Read amplifier circuit
07/30/2003CN1116682C Data output buffer circuit of semiconductor memory device
07/29/2003US6601126 Chip-core framework for systems-on-a-chip
07/29/2003US6601123 Method and apparatus to control the signal development rate of a differential bus
07/29/2003US6600693 Method and circuit for driving quad data rate synchronous semiconductor memory device
07/29/2003US6600691 High frequency range four bit prefetch output data path
07/29/2003US6600690 Sense amplifier for a memory having at least two distinct resistance states
07/29/2003US6600688 Semiconductor memory and method of operating the same
07/29/2003US6600687 Method of compensating for a defect within a semiconductor device
07/29/2003US6600684 Semiconductor storage device
07/29/2003US6600681 Method and apparatus for calibrating DQS qualification in a memory controller
07/29/2003US6600678 Circuit for reading memory elements
07/29/2003US6600676 Nonvolatile semiconductor memory device with a ROM block settable in the write or erase inhibit mode
07/29/2003US6600671 Reduced area sense amplifier isolation layout in a dynamic RAM architecture
07/29/2003US6600361 Semiconductor device
07/29/2003US6600352 Timing signal generating circuit
07/29/2003US6600343 High speed low power input buffer
07/29/2003US6600342 Column decoder of semiconductor memory device
07/29/2003US6600337 Line segmentation in programmable logic devices having redundancy circuitry
07/24/2003WO2003060722A1 Memory system and memory card
07/24/2003US20030140300 (146,130) error correction code utilizing address information
07/24/2003US20030137893 Semiconductor memory system having a data clock system for reliable high-speed data transfers
07/24/2003US20030137892 Semiconductor memory device
07/24/2003US20030137891 Method for writing data bits to a memory array
07/24/2003US20030137886 Cutting patterns for full phase shifting masks
07/24/2003US20030137885 Burst read addressing in a non-volatile memory device
07/24/2003US20030137884 Burst read addressing in a non-volatile memory device
07/24/2003US20030137882 ROM embedded DRAM with bias sensing
07/24/2003US20030137881 Memory control circuit and control system
07/24/2003US20030137878 Reducing the effects of noise in non-volatile memories through multiple reads
07/24/2003US20030137872 Semiconductor memory device and storage method thereof
07/24/2003US20030137865 Non-volatile passive matrix device and method for readout of the same
07/24/2003US20030137863 Semiconductor device
07/24/2003US20030137860 Memory module with integrated bus termination
07/24/2003US20030137323 Electrical or electronic circuit arrangement and associated method
07/24/2003US20030136976 Nonvolatile semiconductor memory with a page mode
07/23/2003EP1329902A1 Method for writing data bits to a memory array
07/23/2003EP1329894A1 Reducing the effects of noise in non-volatile memories through multiple reads
07/23/2003EP1329810A1 Tuple space operations for fine grained system control
07/23/2003EP1328942A1 Method and system for hiding refreshes in a dynamic random access memory
07/23/2003CN1431664A Semiconductor memory
07/22/2003US6598171 Integrated circuit I/O using a high performance bus interface
07/22/2003US6598116 Memory interface using only one address strobe line
07/22/2003US6598099 Data transfer control method, and peripheral circuit, data processor and data processing system for the method
07/22/2003US6597630 Synchronous semiconductor memory device with NOEMI output buffer circuit
07/22/2003US6597628 Auto-disable receive control for DDR receive strobes
07/22/2003US6597627 Clock switching circuitry for avoiding conflict of data handling occuring in a memory
07/22/2003US6597626 Synchronous semiconductor memory device
07/22/2003US6597622 Apparatus and method for operation of multi-bank semiconductor memory device with an up/down counter
07/22/2003US6597620 Storage circuit with data retention during power down
07/22/2003US6597617 Semiconductor device with reduced current consumption in standby state
07/22/2003US6597615 Refresh control for semiconductor memory device
07/22/2003US6597613 Load independent single ended sense amplifier
07/22/2003US6597612 Sense amplifier circuit
07/22/2003US6597611 Memory read circuitry
07/22/2003US6597608 Coding cell of nonvolatile ferroelectric memory device and operating method thereof, and column repair circuit of nonvolatile ferroelectric memory device having the coding cell and method for repairing column
07/22/2003US6597600 Offset compensated sensing for magnetic random access memory
07/22/2003US6597598 Resistive cross point memory arrays having a charge injection differential sense amplifier