Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 7 - Arrangements for writing information into, or reading information out from, a digital store
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
05/2003
05/27/2003US6570794 Twisted bit-line compensation for DRAM having redundancy
05/27/2003US6570792 Bus driving circuit and memory device having same
05/27/2003US6570791 Flash memory with DDRAM interface
05/27/2003US6570440 Direct-timed sneak current cancellation
05/22/2003WO2003043008A1 Digital music player having an encryption function
05/22/2003US20030097534 Memory system using non-distributed command/address clock
05/22/2003US20030097519 Memory subsystem
05/22/2003US20030097513 l/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures
05/22/2003US20030095467 Test circuit for testing semiconductor memory
05/22/2003US20030095465 High area efficient data line architecture
05/22/2003US20030095464 Programmable memory controller and controlling method
05/22/2003US20030095462 Memory device and method of accessing a memory device
05/22/2003US20030095457 Sense amplifier circuits using a single bit line input
05/22/2003US20030095456 Sense amplifier with independent write-back capability for ferroelectric random-access memories
05/22/2003US20030095453 Read amplifier with a low current consumption differential output stage
05/22/2003US20030095444 Semiconductor memory device for providing address access time and data access time at a high speed
05/22/2003US20030095442 Method and apparatus for outputting burst read data
05/22/2003US20030095431 Sense amplifier for multilevel non-volatile integrated memory devices
05/22/2003US20030095430 Semiconductor memory device
05/22/2003US20030095429 Semiconductor memory device
05/22/2003US20030094984 Delay locked loop
05/22/2003US20030094957 Method and logic decision device for generating ferro-electric capacitor reference voltage
05/21/2003EP1313104A1 Semiconductor memory device
05/21/2003EP1312183A1 Apparatus and method for operating a master-slave system with a clock signal and a separate phase signal
05/21/2003EP1312094A1 Method and apparatus for crossing clock domain boundaries
05/21/2003EP1312093A2 Memory device having posted write per command
05/21/2003EP1312092A2 Synchronized write data on a high speed memory bus
05/21/2003EP1312091A1 Memory device and method having data path with multiple prefetch i/o configurations
05/21/2003EP1311962A1 Control circuit for a dram memory
05/21/2003CN1419291A Nonvolatile semiconductor memory
05/21/2003CN1419203A Network rewriting and recording system, and method thereof
05/21/2003CN1419202A Network rewriting and recordinkg system, and method thereof
05/20/2003US6567904 Method and apparatus for automatically detecting whether a memory unit location is unpopulated or populated with synchronous or asynchronous memory devices
05/20/2003US6567898 Memory controller and an information processing apparatus with improved efficiency
05/20/2003US6567339 Semiconductor integrated circuit
05/20/2003US6567338 Fully synchronous pipelined RAM
05/20/2003US6567337 Pulsed circuit topology to perform a memory array write operation
05/20/2003US6567336 Semiconductor memory for logic-hybrid memory
05/20/2003US6567330 Semiconductor memory device
05/20/2003US6567326 Semiconductor memory device
05/20/2003US6567321 Semiconductor memory device using dedicated command and address strobe signal and associated method
05/20/2003US6567320 Data write circuit
05/20/2003US6567317 Controlling output current rambus DRAM
05/20/2003US6567314 Data programming implementation for high efficiency CHE injection
05/20/2003US6567311 Nonvolatile memory system, semiconductor memory, and writing method
05/20/2003US6567298 Semiconductor memory device and control method thereof
05/20/2003US6567297 Method and apparatus for sensing resistance values of memory cells
05/20/2003US6567294 Low power pre-charge high ROM array
05/20/2003US6567290 High-speed low-power semiconductor memory architecture
05/20/2003US6567287 Memory device with row and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays
05/20/2003US6566929 Sense amplifier drive circuit
05/20/2003US6566914 Sense amplifier having reduced Vt mismatch in input matched differential pair
05/20/2003US6566682 Programmable memory address and decode circuits with ultra thin vertical body transistors
05/15/2003WO2003041172A1 Ferroelectric nonvolatile semiconductor memory
05/15/2003WO2003041082A1 Non-volatile memory with temperature-compensated data read
05/15/2003WO2003039289A2 Containers with additional functionality
05/15/2003WO2002099807A3 Method and apparatus for boosting bitlines for low vcc read
05/15/2003WO2002069344A3 Method and apparatus for forcing idle cycles to enable refresh operations in a semiconductor memory
05/15/2003US20030090953 Semiconductor memory card, method of controlling the same and interface apparatus for semiconductor memory card
05/15/2003US20030090952 Delayed locked loop implementation in a synchronous dynamic random access memory
05/15/2003US20030090950 Semiconductor memory device and bit line sensing method thereof
05/15/2003US20030090948 Semiconductor device having memory cells coupled to read and write data lines
05/15/2003US20030090946 Information processing apparatus and recording control method including erroneous-erasure prevention feature
05/15/2003US20030090945 Memory device for use in high-speed block pipelined Reed-Solomon decoder, method of accessing the memory device, and Reed-Solomon decoder having the memory device
05/15/2003US20030090944 Semiconductor memory device
05/15/2003US20030090939 Nonvolatile memory device with parallel and serial functioning mode and selectable communication protocol
05/15/2003US20030090307 Circuit and method for generating output control signal in synchronous semiconductor memory device
05/15/2003US20030090294 Data-sampling strobe signal generator and input buffer using the same
05/15/2003US20030090287 Input buffer with automatic switching point adjustment circuitry, and synchronous DRAM device including same
05/15/2003US20030089941 Method for stabilizing or offsetting voltage in an integrated circuit
05/15/2003US20030089940 Capacitor comprising a layer of conductive material having a first portion and a second portion arranged in a pattern relative to one another to provide maximum capacitance per semiconductor die area; e.g. pattern of interleaved combs
05/15/2003US20030089777 Method and system for authoring and playback of audio coincident with label detection
05/14/2003EP0954864B1 Zero power high speed configuration memory
05/14/2003CN1417969A Semicoductor device
05/14/2003CN1417805A Device and method for controlling active terminal resistance in memory system
05/14/2003CN1417804A Semicoductor memory device, its control method and semiconductor device control method
05/14/2003CN1417803A Magnetic memory with SOI base board and its making process
05/13/2003US6564303 Dual port memory for digital signal processor
05/13/2003US6564288 Memory controller with temperature sensors
05/13/2003US6564287 Semiconductor memory device having a fixed CAS latency and/or burst length
05/13/2003US6564285 Synchronous interface for a nonvolatile memory
05/13/2003US6564281 Synchronous memory device having automatic precharge
05/13/2003US6563760 Circuit and method for generating internal command signals in a semiconductor memory device
05/13/2003US6563759 Semiconductor memory device
05/13/2003US6563758 Multiple ports memory-cell structure
05/13/2003US6563756 Memory device with reduced refresh noise
05/13/2003US6563754 DRAM circuit with separate refresh memory
05/13/2003US6563753 Sense amplifier with independent write-back capability for ferroelectric random-access memories
05/13/2003US6563748 Semiconductor device having mechanism capable of high-speed operation
05/13/2003US6563747 Integrated data input sorting and timing circuit for double data rate (DDR) dynamic random access memory (DRAM) devices
05/13/2003US6563744 Semiconductor memory device
05/13/2003US6563743 Semiconductor device having dummy cells and semiconductor device having dummy cells for redundancy
05/13/2003US6563738 Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics
05/13/2003US6563737 Reading circuit for semiconductor non-volatile memories
05/13/2003US6563344 Buffer circuit for the reception of a clock signal
05/08/2003WO2003038832A1 Semiconductor storage device
05/08/2003WO2003038829A2 Storage assembly
05/08/2003WO2003038567A2 Digital audio device
05/08/2003US20030088818 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same
05/08/2003US20030088785 ID installable LSI, secret key installation method, LSI test method, and LSI development method
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