Patents
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
08/2006
08/02/2006CN1811987A Bit line voltage supply circuit in semiconductor memory device and voltage supplying method therefor
08/02/2006CN1811986A Memory cell power switching circuit in semiconductor memory device and method for applying memory cell power voltage
08/02/2006CN1811984A Spin-injection magnetic random access memory and write-in method
08/02/2006CN1811982A Method of driving a program operation in a nonvolatile semiconductor memory device
08/02/2006CN1811981A Integrate circuit
08/02/2006CN1811980A Memory circuit receivers activated by enable circuit
08/02/2006CN1811979A Improved sensing amplifier
08/02/2006CN1811978A Method for reducing power consumption of memory in integrated circuit
08/02/2006CN1811955A Tamper-proof content-playback system
08/02/2006CN1811732A Pre-record storage capable of being set by user
08/02/2006CN1267804C Memory systems and methods of operating the same
08/01/2006US7085975 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same
08/01/2006US7085974 Semiconductor device, method of testing the same and electronic instrument
08/01/2006US7085946 Backup memory control unit with reduced current consumption having normal self-refresh and unsettled modes of operation
08/01/2006US7085912 Sequential nibble burst ordering for data
08/01/2006US7085906 Memory device
08/01/2006US7085905 Memory data stretcher
08/01/2006US7085882 SRAM-compatible memory and method of driving the same
08/01/2006US7085881 Semiconductor memory device
08/01/2006US7085874 Synchronous/asynchronous bridge circuit for improved transfer of data between two circuits
08/01/2006US7085193 Clock-synchronous semiconductor memory device
08/01/2006US7085192 Semiconductor integrated circuit device
08/01/2006US7085191 Simulating a floating wordline condition in a memory device, and related techniques
08/01/2006US7085188 Semiconductor memory device, control method thereof, and control method of semiconductor device
08/01/2006US7085187 Semiconductor storage device
08/01/2006US7085186 Method for hiding a refresh in a pseudo-static memory
08/01/2006US7085185 Circuit and method for controlling an access to an integrated memory
08/01/2006US7085184 Delayed bitline leakage compensation circuit for memory devices
08/01/2006US7085183 Adaptive algorithm for MRAM manufacturing
08/01/2006US7085182 Fuse blowing interface for a memory chip
08/01/2006US7085180 Method and structure for enabling a redundancy allocation during a multi-bank operation
08/01/2006US7085179 Integrated circuit having a non-volatile memory cell transistor as a fuse device
08/01/2006US7085178 Low-power memory write circuits
08/01/2006US7085177 Maximum swing thin oxide levelshifter
08/01/2006US7085176 On-chip power-on voltage initialization
08/01/2006US7085175 Word line driver circuit for a static random access memory and method therefor
08/01/2006US7085174 Semiconductor memory device with current driver providing bi-directional current to data write line
08/01/2006US7085173 Write driver circuit for memory array
08/01/2006US7085172 Data storage apparatus, data storage control apparatus, data storage control method, and data storage control program
08/01/2006US7085171 Semiconductor memory device
08/01/2006US7085169 Flash memory device capable of reducing read time
08/01/2006US7085164 Programming methods for multi-level flash EEPROMs
08/01/2006US7085161 Non-volatile semiconductor memory with large erase blocks storing cycle counts
08/01/2006US7085159 Highly compact non-volatile memory and method therefor with internal serial buses
08/01/2006US7085158 Nonvolatile semiconductor memory device and one-time programming control method thereof
08/01/2006US7085156 Semiconductor memory device and method of operating same
08/01/2006US7085155 Secured phase-change devices
08/01/2006US7085154 Device and method for pulse width control in a phase change memory device
08/01/2006US7085149 Method and apparatus for reducing leakage current in a read only memory device using transistor bias
08/01/2006US7085148 Semiconductor memory device
08/01/2006US7084690 Semiconductor integrated circuit device
08/01/2006US7084686 System and method for open-loop synthesis of output clock signals having a selected phase relative to an input clock signal
08/01/2006US7084673 Output driver with pulse to static converter
08/01/2006US7084672 Sense amplifier circuit for content addressable memory device
08/01/2006US7084489 Computer system including at least one stress balanced semiconductor package
08/01/2006CA2534330A1 Read and/or write detection system for an asynchronous memory array
07/2006
07/27/2006WO2006078505A2 A non-volatile memory cell comprising a dielectric layer and a phase change material in series
07/27/2006WO2006077047A1 Near pad ordering logic
07/27/2006WO2006077046A1 Intelligent memory array switching logic
07/27/2006WO2006047089A3 Memory output data systems and methods with feedback
07/27/2006US20060168470 Random access memory with post-amble data strobe signal noise rejection
07/27/2006US20060168408 System and method for interleaving sdram device access requests
07/27/2006US20060167958 Tree system diagram output method, computer program and recording medium
07/27/2006US20060164906 Semiconductor integrated circuit and IC card
07/27/2006US20060164903 Semiconductor memory device having self refresh mode and related method of operation
07/27/2006US20060164902 Pseudo-synchronization of the transportation of data across asynchronous clock domains
07/27/2006US20060164898 Exploiting a statistical distribution of the values of an electrical characteristic in a population of auxiliary memory cells for obtaining reference cells
07/27/2006US20060164897 Semiconductor storage device having page copying function
07/27/2006US20060164896 Memory cell array biasing method and a semiconductor memory device
07/27/2006US20060164895 Semiconductor storage device
07/27/2006US20060164892 Reduction of fusible links and associated circuitry on memory dies
07/27/2006US20060164140 Generating multi-phase clock signals using hierarchical delays
07/27/2006US20060163645 EEPROM With Split Gate Source Side Injection
07/27/2006DE4308665B4 DRAM mit einer bidirektionalen globalen Bitleitung DRAM with a bidirectional global bit line
07/27/2006DE102006001857A1 Memory device e.g. dynamic random access memory device, has input/output buffer stage with terminal logic that is configured in order to receive data bits sequentially on data terminals with data frequency during writing operation
07/27/2006DE102005001892A1 Steuereinheit Control unit
07/26/2006EP1684302A2 Recording medium editing apparatus based on content supply source
07/26/2006EP1684301A2 Recording medium editing apparatus based on content supply source
07/26/2006EP1684300A2 MPEG portable sound reproducing system and a reproducing method thereof
07/26/2006EP1683291A1 Content distribution systems and methods
07/26/2006EP1683156A1 Internal voltage reference for memory interface
07/26/2006EP1604371B1 Memory system having sequentially performed fast and slow data reading mechanisms
07/26/2006EP1471644B1 Logical operation circuit and logical operation method
07/26/2006CN1809929A MRAM architecture with a bit line located underneath the magnetic tunneling junction device
07/26/2006CN1808718A Storage unit and operation methods for array of electric charge plunged layer
07/26/2006CN1808624A Shift cache unit and associated signal drive circuit and display system
07/26/2006CN1808622A Nonvolatile memory devices and programming methods using subsets of columns
07/26/2006CN1808620A Stack cache
07/26/2006CN1808601A Method and apparatus of controlling buffer memory with self-judging and reset capability
07/26/2006CN1266611C Internal memory module and method for operating memory module in data memory system
07/25/2006US7082491 Memory device having different burst order addressing for read and write operations
07/25/2006US7082256 Recording medium editing apparatus based on content supply source
07/25/2006US7082077 Control method of semiconductor memory device and semiconductor memory device
07/25/2006US7082076 Memory module with hierarchical functionality
07/25/2006US7082075 Memory device and method having banks of different sizes
07/25/2006US7082074 Semiconductor device having a power down mode
07/25/2006US7082073 System and method for reducing power consumption during extended refresh periods of dynamic random access memory devices
07/25/2006US7082072 Semiconductor memory device with refreshment control
07/25/2006US7082071 Integrated DDR/SDR flow control managers that support multiple queues and MUX, DEMUX and broadcast operating modes
07/25/2006US7082070 Temperature detection circuit and temperature detection method