Patents
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
05/2006
05/03/2006CN1766850A Memory card having a storage cell and method of controlling the same
05/03/2006CN1766411A Memory-based audio player with illumination
05/03/2006CN1254917C Input buffer circuit
05/02/2006US7039847 Coding-decoding device and method for conversion of binary sequences
05/02/2006US7039838 Method for testing a circuit unit to be tested and test apparatus
05/02/2006US7039822 Integrated circuit memory architecture with selectively offset data and address delays to minimize skew and provide synchronization of signals at the input/output section
05/02/2006US7039818 Low leakage SRAM scheme
05/02/2006US7039786 Memory device and recording and/or reproducing apparatus employing this memory device
05/02/2006US7039780 Digital camera memory system
05/02/2006US7039759 Portable data storage device
05/02/2006US7039753 Memory device and recording and/or reproducing apparatus using the same
05/02/2006US7039147 Delay locked loop circuitry for clock delay adjustment
05/02/2006US7038972 Double data rate synchronous dynamic random access memory semiconductor device
05/02/2006US7038971 Multi-clock domain data input-processing device having clock-receiving locked loop and clock signal input method thereof
05/02/2006US7038970 Programming and evaluating through PMOS injection
05/02/2006US7038969 Semiconductor memory having a spare memory cell
05/02/2006US7038968 Self-refresh control circuit
05/02/2006US7038967 Semiconductor apparatus capable of performing refresh control
05/02/2006US7038966 Memory device and method having data path with multiple prefetch I/O configurations
05/02/2006US7038965 Pointer generator for stack
05/02/2006US7038964 Access to a common memory in which a priority access to a non-active bank is prepared during a non-priority access to a different bank
05/02/2006US7038963 Current sense amplifier circuits having a bias voltage node for adjusting input resistance
05/02/2006US7038962 Semiconductor integrated circuit
05/02/2006US7038961 Semiconductor device
05/02/2006US7038960 High speed and high precision sensing for digital multilevel non-volatile memory system
05/02/2006US7038959 MRAM sense amplifier having a precharge circuit and method for sensing
05/02/2006US7038958 Dual stage DRAM memory equalization
05/02/2006US7038957 Semiconductor memory device for testifying over-driving quantity depending on position
05/02/2006US7038955 Semiconductor device and testing apparatus for semiconductor device
05/02/2006US7038953 Memory interface control circuit and memory interface control method
05/02/2006US7038941 Magnetic memory storage device
05/02/2006US7038936 Reading circuit for reading a memory cell
05/02/2006US7038927 High speed data bus
05/02/2006US7038691 Two-dimensional buffer pages using memory bank alternation
05/02/2006US7038486 Semiconductor integrated circuit device
05/02/2006US7038469 Method of determining localized electron tunneling in a capacitive structure
05/02/2006US7036733 Method for responding a reading command in an automatically adaptive memory card and memory card controller
05/02/2006CA2238309C Method and apparatus for securing data stored in semiconductor memory cells
05/02/2006CA2223222C Data-bit redundancy for semiconductor memories
04/2006
04/27/2006WO2006042643A1 Dqs for data from a memory array
04/27/2006WO2005109437A3 Pfet nonvolatile memory
04/27/2006US20060090056 Dynamically setting burst length and type
04/27/2006US20060087909 Semiconductor integrated circuit device
04/27/2006US20060087905 Voltage translator for multiple voltage operations
04/27/2006US20060087904 Memory device capable of refreshing data using buffer and refresh method thereof
04/27/2006US20060087903 Refresh control method of a semiconductor memory device and semiconductor memory device
04/27/2006US20060087902 Selective bank refresh
04/27/2006US20060087901 Device for controlling temperature compensated self-refresh period
04/27/2006US20060087900 Semi-conductor component, as well as a process for the in-or output of test data
04/27/2006US20060087897 Memory output data systems and methods with feedback
04/27/2006US20060087895 Memory circuit with flexible bitline-related and/or wordline-related defect memory cell substitution
04/27/2006US20060087893 Storage device and information processing system
04/27/2006US20060087307 Single pin multilevel integrated circuit test interface
04/27/2006DE202006002071U1 Data medium, e.g. chip card, smart card, secure multimedia card or USB storage medium has non-volatile memory with array elements, each associated with different buffer memory start address and configured for storage of buffer memory state
04/27/2006DE102005051206A1 Memory system, has memory controller controlling set of memory devices, providing command signal and chip selecting signal to memory devices, and outputting output data strobe signal of memory devices
04/27/2006DE102005049246A1 Kombinierter Empfänger und Latch Combined receiver and latch
04/27/2006DE102004050104A1 Halbleiter-Bauelement, sowie Verfahren zum Auslesen von Testdaten A semiconductor device, and method of reading test data
04/27/2006DE102004022327B4 Integrierter Halbleiterspeicher Integrated semiconductor memory
04/26/2006EP1649468A1 Compensating a long read time of a memory device in data comparison and write operations
04/26/2006CN1763727A Processor memory access method and access apparatus thereof
04/26/2006CN1253896C Dynamic random access memory and method used for single level readout
04/26/2006CN1253893C Method of guiding ROM to realize write protection
04/25/2006US7036056 Semiconductor memory device having time reduced in testing of memory cell data reading or writing, or testing of sense amplifier performance
04/25/2006US7036053 Two dimensional data eye centering for source synchronous data transfers
04/25/2006US7035965 Flash memory with data decompression
04/25/2006US7035964 Method and device for securing data when altering the storage contents of control units
04/25/2006US7035366 Delay locked loop circuit and its control method
04/25/2006US7035164 Semiconductor memory device with a bypass circuit for verifying the characteristics of an internal clock signal
04/25/2006US7035163 Asynchronously-resettable decoder with redundancy
04/25/2006US7035161 Semiconductor integrated circuit
04/25/2006US7035160 Circuit
04/25/2006US7035158 Semiconductor memory with self fuse programming
04/25/2006US7035157 Temperature-dependent DRAM self-refresh circuit
04/25/2006US7035156 Semiconductor memory device control method thereof, and control method of semiconductor device
04/25/2006US7035155 Dynamic memory management
04/25/2006US7035154 Semiconductor memory device and its test method as well as test circuit
04/25/2006US7035153 Semiconductor memory device of bit line twist system
04/25/2006US7035152 System and method for redundancy memory decoding
04/25/2006US7035150 Memory device with column select being variably delayed
04/25/2006US7035149 Semiconductor memory apparatus and activation signal generation method for sense amplifier
04/25/2006US7035148 Output driver capable of controlling slew rate of output signal according to operating frequency information or CAS latency information
04/25/2006US7035145 Programming methods for multi-level flash EEPROMs
04/25/2006US7035137 Semiconductor memory device having memory cells including ferromagnetic films and control method thereof
04/25/2006US7035132 Memory architecture for increased speed and reduced power consumption
04/25/2006US7035131 Dynamic random access memory cell leakage current detector
04/25/2006US7034792 RAM-incorporated driver, and display unit and electronic equipment using the same
04/25/2006US7034603 Floating-gate reference circuit
04/25/2006US7034575 Variable impedence output buffer
04/25/2006US7034565 On-die termination circuit and method for reducing on-chip DC current, and memory system including memory device having the same
04/20/2006WO2004086406A8 Sense amplifier systems and a matrix-addressable memory device provided therewith
04/20/2006US20060085589 Status register to improve initialization of a synchronous memory
04/20/2006US20060085578 Flash memory card with enhanced operating mode detection and user-friendly interfacing system
04/20/2006US20060083094 Method and apparatus for controlling refresh operations in a dynamic memory device
04/20/2006US20060083093 Non-volatile configuration data storage for a configurable memory
04/20/2006US20060083092 Dynamical adaptation of memory sense electronics
04/20/2006US20060083091 Semiconductor storage device precharging/discharging bit line to read data from memory cell
04/20/2006US20060083087 Apparatus and method for semiconductor device repair with reduced number of programmable elements
04/20/2006US20060083083 Method and apparatus for synchronization of row and column access operations
04/20/2006US20060083082 DQS for data from a memory array
04/20/2006US20060083081 Memory system, memory device, and output data strobe signal generating method