Patents
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
08/2006
08/31/2006US20060193177 Position based erase verification levels in a flash memory device
08/31/2006US20060192600 Synchronous output buffer, synchronous memory device and method of testing access time
08/31/2006DE69833093T2 Schwebende Bitleitungen Prüfmodus mit digital steuerbaren Bitleitungen-Abgleichschaltungen Pending bit test mode with digitally controllable bit lines matching circuits
08/31/2006DE19924288B4 Integrierter Speicher Built-in Memory
08/31/2006DE19916348B4 Synchrone Halbleiter-Speichervorrichtung mit Reaktion auf ein externes Maskiersignal zum Erzwingen des Eintritts eines Datenanschlusses in einen Hochimpedanzzustand und ihr Steuerverfahren Synchronous semiconductor memory device having a reaction to an external masking to force the occurrence of a data connection to a high-impedance state and its control method
08/31/2006DE10249869B4 Magnetische Dünnfilmspeichervorrichtung zum Durchführen eines Datenschreibvorgangs durch Anlegen eines Magnetfelds Thin film magnetic memory device for performing a data write operation by applying a magnetic field
08/30/2006EP1696600A2 Prediction of an optimal sampling point for clock resynchronization in a source synchronous data channel
08/30/2006EP1696599A2 Source synchronous communication channel interface receive logic
08/30/2006EP1642297A4 Data strobe synchronization circuit and method for double data rate, multi-bit writes
08/30/2006EP1634172A4 Fault tolerant data storage circuit
08/30/2006EP1402641B1 Method and apparatus for a clock circuit
08/30/2006CN2812222Y SCART interface convenient for EEROM data modification and software update
08/30/2006CN2812220Y A portable multimedia video & audio player
08/30/2006CN1826731A Method and apparatus for encoding of low voltage swing signals
08/30/2006CN1826658A Compensating a long read time of a memory device in data comparison and write operations
08/30/2006CN1825493A Memory circuit
08/30/2006CN1825489A 半导体存储装置 The semiconductor memory device
08/30/2006CN1825485A Multi-pattern multi-stage charge pump
08/30/2006CN1825480A Semiconductor memory devices having signal delay controller and methods performed therein
08/30/2006CN1825476A 半导体存储器装置 The semiconductor memory device
08/30/2006CN1825472A Audio-frequency playing terminal
08/30/2006CN1825471A 同步与数据恢复装置 Synchronization and data recovery means
08/30/2006CN1825470A Method for operating page buffer of nonvolatile memory device
08/30/2006CN1825469A Memory array circuit with word line timing control for read operations and write operations
08/30/2006CN1825468A Semiconductor storage system and method for transmission of write and read data
08/30/2006CN1825466A Memory device, memory controller and method for operating the same
08/30/2006CN1825271A 存储装置 Storage device
08/30/2006CN1272802C Circuit and method for improving speed and stability of sensing amplifier
08/30/2006CN1272801C Semiconductor storage device
08/29/2006US7100090 Semiconductor memory device having a test circuit
08/29/2006US7099585 Memory circuit with an optical input
08/29/2006US7099558 Recording medium editing apparatus based on content supply source
08/29/2006US7099425 Adjustment circuit and method for tuning of a clock signal
08/29/2006US7099233 Parallel asynchronous propagation pipeline structure and methods to access multiple memory arrays
08/29/2006US7099232 Delay locked loop device
08/29/2006US7099231 Interleaving memory blocks to relieve timing bottleneck in a multi-queue first-in first-out memory system
08/29/2006US7099226 Functional register decoding system for multiple plane operation
08/29/2006US7099222 Refresh operation type semiconductor memory device capable of smoothly transferring special state to normal active state and its driving method
08/29/2006US7099221 Memory controller method and system compensating for memory cell data losses
08/29/2006US7099220 Methods for erasing flash memory
08/29/2006US7099219 Multi read port bit line
08/29/2006US7099218 Differential current evaluation circuit and sense amplifier circuit for evaluating a memory state of an SRAM semiconductor memory cell
08/29/2006US7099217 Semiconductor memory with sense amplifier equalizer having transistors with gate oxide films of different thicknesses
08/29/2006US7099216 Single cycle read/write/writeback pipeline, full-wordline I/O DRAM architecture with enhanced write and single ended sensing
08/29/2006US7099215 Systems, methods and devices for providing variable-latency write operations in memory devices
08/29/2006US7099214 Semiconductor memory device
08/29/2006US7099213 Page buffer for flash memory device
08/29/2006US7099212 Embedded ROM device using substrate leakage
08/29/2006US7099210 Semiconductor memory device having memory cells with floating gates and memory cell threshold voltage control method
08/29/2006US7099209 Semiconductor memory device having repair circuit
08/29/2006US7099208 Semiconductor memory automatically carrying out refresh operation
08/29/2006US7099207 Semiconductor memory device and method for masking predetermined area of memory cell array during write operation
08/29/2006US7099206 High density bitline selection apparatus for semiconductor memory devices
08/29/2006US7099204 Current sensing circuit with a current-compensated drain voltage regulation
08/29/2006US7099203 Circuit and method for writing a binary value to a memory cell
08/29/2006US7099201 Multifunctional latch circuit for use with both SRAM array and self test device
08/29/2006US7099188 Bit line reference circuits for binary and multiple-bit-per-cell memories
08/29/2006US7099186 Double-decker MRAM cells with scissor-state angled reference layer magnetic anisotropy and method for fabricating
08/29/2006US7099179 Conductive memory array having page mode and burst mode write capability
08/29/2006US7099177 Nonvolatile ferroelectric memory device having power control function
08/29/2006US7099175 Semiconductor memory integrated circuit
08/29/2006US7099173 Stacked layered type semiconductor memory device
08/29/2006US7098699 Buffer circuit device supplying a common mode voltage applicable to a next-stage circuit receiving output signals of the buffer circuit device
08/29/2006US7098698 Semiconductor integrated circuit device and sense amplifier of memory
08/24/2006WO2006089313A2 Register read for volatile memory
08/24/2006US20060190677 Sequential nibble burst ordering for data
08/24/2006US20060190638 Asynchronous jitter reduction technique
08/24/2006US20060188051 Delay locked loop circuitry for clock delay adjustment
08/24/2006US20060187742 Nonvolatile ferroelectric memory and control device using the same
08/24/2006US20060187736 Non-volatile memory device conducting comparison operation
08/24/2006US20060187734 Semiconductor integrated circuit and IC card
08/24/2006US20060187732 Memory circuit with automatic precharge function, and integrated circuit device with automatic internal command function
08/24/2006US20060187731 Semiconductor memory device
08/24/2006US20060187730 Semiconductor device and display device utilizing the same
08/24/2006US20060187729 Source synchronous communication channel interface receive logic
08/24/2006US20060187728 Integrated semiconductor memory
08/24/2006US20060187727 Self-addressed subarray precharge
08/24/2006US20060187726 Memory bus checking procedure
08/24/2006US20060187725 Semiconductor memory device
08/24/2006US20060187722 Panel assembly for display device, display device including the same, and repairing method for display device
08/24/2006US20060187721 Random access memory including selective activation of select line
08/24/2006US20060187720 Semiconductor device
08/24/2006US20060187719 Semiconductor package, ID generating system thereof, ID recognizing system thereof, ID recognition method thereof, semiconductor integrated circuit chip, ID generating system thereof, ID recognizing system thereof, and ID recognition method thereof
08/24/2006US20060187704 Spin based sensor device
08/24/2006US20060187673 Offset compensated sensing for magnetic random access memory
08/24/2006US20060186915 Method and apparatus for calibrating a multi-level current mode driver having a plurality of source calibration signals
08/24/2006DE102005011368A1 Stacked bus system, has modules accessing point-to-point resources e.g. clock signals, where one of modules is assigned to one of resources and has allocation device that is designed to allocate another resource to another module
08/24/2006DE102005007600A1 Controller, e.g. for double data rate-dynamic random access memory, has synchronization and actuation medium actuating output of clock signals to point of time synchronous with next following flank of basic timing signal directly
08/24/2006DE102005006679A1 Verfahren zur Beseitigung der auf einem tragbaren Datenträger gespeicherten Informationen A process for the removal of the information stored on a portable data carrier
08/23/2006EP1693853A2 Read and/or write detection system for an asynchronous memory array
08/23/2006EP1595261A4 Dram output circuitry supporting sequential data capture to reduce core access times
08/23/2006EP1496519B1 Encoding method and memory apparatus
08/23/2006CN2810073Y Portable digital flat panel sound box
08/23/2006CN2809805Y Card-reading base for USB connection terminal specification memory card
08/23/2006CN1822234A Nonvolatile semiconductor memory device
08/23/2006CN1822227A Multi-level cell memory device and associated read method
08/23/2006CN1822225A Semiconductor memory device
08/23/2006CN1822224A Memory device capable of refreshing data using buffer and refresh method thereof
08/23/2006CN1822223A Memory circuit
08/23/2006CN1822222A Semiconductor device employing fuse circuit and method for selecting fuse circuit system