Patents
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
10/2006
10/05/2006US20060220101 Highly Compact Non-Volatile Memory and Method Therefor With Internal Serial Buses
10/05/2006DE102006016247A1 Memory e.g. programmable ROM, for data processing system e.g. mobile telephone, has control logic unit to control memory core such that data reading periods are obtained from address and command information of core
10/05/2006DE102006014558A1 Flash memory has control logic circuit that controls buffer memories and nonvolatile memory core based on address and command information in second register, and first register for storing address information for next reading operation
10/05/2006DE102006004848A1 Verfahren und Vorrichtung zum Variieren eines aktiven Arbeitszyklus einer Wortleitung Method and apparatus for varying an active duty cycle of a word line
10/05/2006DE102005052273A1 Mehrchippackungsbauelement und Treiberverfahren hierfür Multi-chip package device and driving method therefor
10/05/2006DE102005049987A1 Data output buffer for use in semiconductor memory device, has buffer unit that outputs data from buffer input line to buffer output line based on buffer enabling signal obtained from delay control unit
10/05/2006DE102005042142A1 High-speed, low-power input buffer memory for use in integrated circuit, has voltage compensation units for inducing voltage compensation between input voltage signal, pull-up transistor and pull-down transistor
10/05/2006DE102005014723A1 Electronic switching device has reference signal port connected to signal blocking unit for blocking unwanted signals and to ensure that only predetermined reference signal is supplied to electronic switching units
10/05/2006DE10037706B4 Schaltung zum Betreiben eines nichtflüchtigen ferroelektrischen Speichers Circuit for operating a nonvolatile ferroelectric memory
10/04/2006EP1708203A1 Nonvolatile memory device and method for storing status information using multiple strings
10/04/2006EP1567938B1 Memory system comprising a plurality of memory controllers and method for synchronizing the same
10/04/2006CN1842963A Clock signal input/output device for correcting clock signals
10/04/2006CN1842875A Semiconductor memory component and method for operating said component
10/04/2006CN1842871A Accelerated life test of MRAM cells
10/04/2006CN1842843A Method and apparatus for read bitline clamping for gain cell DRAM devices
10/04/2006CN1841566A Method for current sense amplifier calibration in MRAM devices
10/04/2006CN1841563A Page buffer circuit of flash memory device
10/04/2006CN1841557A Using a bit specific reference level to read a memory
10/04/2006CN1841554A High-speed, low-power input buffer for integrated circuit devices
10/04/2006CN1278239C Storage system and storage card
10/03/2006US7117421 Transparent error correction code memory system and method
10/03/2006US7117409 Multi-port memory testing method utilizing a sequence folding scheme for testing time reduction
10/03/2006US7117408 Method and system of testing data retention of memory
10/03/2006US7117407 Method for testing a semiconductor memory having a plurality of memory banks
10/03/2006US7117382 Variably controlled delay line for read data capture timing window
10/03/2006US7117381 Control signal generation circuit and data transmission circuit having the same
10/03/2006US7117332 Window-based flash memory storage system and management and access methods thereof
10/03/2006US7117321 System and method for interleaving SDRAM device access requests
10/03/2006US7117307 Memory controlling apparatus performing the writing of data using address line
10/03/2006US7117292 Apparatus and method to switch a FIFO between strobe sources
10/03/2006US7116744 Clock recovery circuit and receiver circuit for improving the error rate of signal reproduction
10/03/2006US7116604 Semiconductor memory device and method for selecting multiple word lines in a semiconductor memory device
10/03/2006US7116603 Non-volatile semiconductor storage device performing ROM read operation upon power-on
10/03/2006US7116602 Method and system for controlling refresh to avoid memory cell data losses
10/03/2006US7116601 Pseudo-synchronization of the transportation of data across asynchronous clock domains
10/03/2006US7116600 Memory device having terminals for transferring multiple types of data
10/03/2006US7116599 High speed FIFO synchronous programmable full and empty flag generation
10/03/2006US7116598 Semiconductor memory
10/03/2006US7116597 High precision reference devices and methods
10/03/2006US7116596 Method of apparatus for enhanced sensing of low voltage memory
10/03/2006US7116595 Thin film magnetic memory device having a magnetic tunnel junction
10/03/2006US7116594 Sense amplifier circuits and high speed latch circuits using gated diodes
10/03/2006US7116593 Storage device
10/03/2006US7116591 Redundancy circuits and memory devices having a twist bitline scheme and methods of repairing defective cells in the same
10/03/2006US7116589 Per-bit set-up and hold time adjustment for double-data rate synchronous DRAM
10/03/2006US7116588 Low supply voltage temperature compensated reference voltage generator and method
10/03/2006US7116586 Non-volatile semiconductor memory device and semiconductor disk device
10/03/2006US7116585 Memory systems and methods
10/03/2006US7116578 Non-volatile memory device and data storing method
10/03/2006US7116570 Access circuit and method for allowing external test voltage to be applied to isolated wells
10/03/2006US7115941 Semiconductor memory element, semiconductor memory device and method of fabricating the same
10/03/2006US7115928 Dual-damascene bit line structures for microelectronic devices and methods of fabricating microelectronic devices
10/03/2006US7115901 Non-volatile electromechanical field effect devices and circuits using same and methods of forming same
09/2006
09/28/2006WO2006102391A2 Temperature compensation of thin film diode voltage threshold in memory sensing circuit
09/28/2006WO2006102390A1 Current sensing circuit with a current-compensated drain voltage regulation
09/28/2006WO2006101984A2 Internally generating patterns for testing in an integrated circuit device
09/28/2006US20060218469 Low power cost-effective ECC memory system and method
09/28/2006US20060218408 System and method for user authentication employing portable handheld electronic devices
09/28/2006US20060215481 System and method for re-ordering memory references for access to memory
09/28/2006US20060215475 Wordline enable circuit in semiconductor memory device and method thereof
09/28/2006US20060215474 Power saving refresh scheme for DRAMs with segmented word line architecture
09/28/2006US20060215473 Circuit for data bit inversion
09/28/2006US20060215472 Memory device having shared open bit line sense amplifier architecture
09/28/2006US20060215471 Single transistor sensing and double transistor sensing for flash memory
09/28/2006US20060215468 Semiconductor memory device
09/28/2006US20060215467 Method of increasing data setup and hold margin in case of non-symmetrical PVT
09/28/2006US20060215466 Methods and systems for generating latch clock used in memory reading
09/28/2006US20060215465 Circuits and methods for providing low voltage, high performance register files
09/28/2006US20060215463 Memory device with a ramp-like voltage biasing structure and reduced number of reference cells
09/28/2006US20060215462 Buffer circuit and memory system for selectively outputting data strobe signal according to number of data bits
09/28/2006US20060215452 NROM flash memory cell with integrated DRAM
09/28/2006US20060214716 Clock signal input/output device for correcting clock signals
09/28/2006DE19941196B4 Zweikanal-FIFO mit synchronisierten Lese- und Schreibzeigern Two channel FIFO with synchronized read and write pointers
09/28/2006DE19904388B4 Halbleiterspeichervorrichtung mit Pulldown-Funktion für unausgewählte Bitleitungen A semiconductor memory device with pulldown function for unselected bit lines
09/28/2006DE10317279B4 Verzögerungsschaltung Delay circuit
09/28/2006DE102005013238A1 Transfer of control information for adjusting the parameter of driver in data interface of RAM, involves transferring control information with control bits in appropriate sequence with respect to data bits from controller to RAM
09/28/2006DE102005013237A1 Memory e.g. dynamic RAM, operation holding time determining device, has counter reporting end of holding time on counting desired number of pulses, and adjusting unit provided over external connection of memory to adjust number of pulses
09/28/2006DE10034699B4 Leseverstärker in einem nichtflüchtigen ferroelektrischen Speicher Sense amplifier in a non-volatile ferroelectric memory
09/27/2006EP1705664A2 Multi-function remote controller
09/27/2006EP1705663A2 Semiconductor memory and system apparatus
09/27/2006EP1704571A1 Non-volatile memory and method with block management system
09/27/2006EP1704570A2 Low-power compiler-programmable memory with fast access timing
09/27/2006EP1377982B1 Multiple bit prefetch output data path
09/27/2006EP1029279B1 Data storage device
09/27/2006CN2822077Y Sports type MP3 player
09/27/2006CN2821775Y Movable data storage
09/27/2006CN1838318A Semiconductor memory component, system possessing same and method for operating the component
09/27/2006CN1838317A Device for defining wait time in storage circuit
09/27/2006CN1838314A Boosted voltage generating circuit and method in semiconductor memory device
09/27/2006CN1838313A Method and circuit for sensing output from memory cell
09/27/2006CN1838312A word line voltage compensation method for write current in phase change memory array
09/27/2006CN1838311A Memory device for serial transmission interface and error correction method thereof
09/27/2006CN1838310A Memory subsystem and its method for generating latch clock
09/27/2006CN1838309A Modulated information transmitting method and device for ram module data interface drive
09/27/2006CN1838308A Method and device for varying an active duty cycle of a wordline
09/27/2006CN1838307A Chip to chip interface including assymetrical transmission impedances
09/27/2006CN1277354C Input and output driver
09/26/2006US7114025 Semiconductor memory having test function for refresh operation
09/26/2006US7113446 Latch circuit and synchronous memory including the same
09/26/2006US7113442 Non-volatile semiconductor memory, semiconductor device and charge pump circuit