Patents
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
11/2006
11/01/2006CN1855295A Clock data recovery circuit with circuit loop disablement
11/01/2006CN1855294A Mobile communication terminal having the function of playing music and music selection method thereof
11/01/2006CN1855293A 半导体存储器装置 The semiconductor memory device
11/01/2006CN1855291A Memory rank decoder for a multi-rank dual inline memory module(DIMM)
11/01/2006CN1855273A Reproducing device, setting changing method, and setting changing device
11/01/2006CN1283005C Semiconductor memory device
11/01/2006CN1282644C Indane or indoline derivative
10/2006
10/31/2006US7130984 First-in first-out memory system with shift register fill indication
10/31/2006US7130241 Semiconductor memory device having different synchronizing timings depending on the value of CAS latency
10/31/2006US7130239 Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure
10/31/2006US7130237 Control circuit for stable exit from power-down mode
10/31/2006US7130236 Low power delay controlled zero sensitive sense amplifier
10/31/2006US7130235 Method and apparatus for a sense amplifier
10/31/2006US7130234 Semiconductor device
10/31/2006US7130233 Sensing circuit for single bit-line semiconductor memory device
10/31/2006US7130232 Integrated circuit devices having multiple precharge circuits and methods of operating the same
10/31/2006US7130231 Method, apparatus, and computer program product for implementing enhanced DRAM interface checking
10/31/2006US7130230 Systems for built-in-self-test for content addressable memories and methods of operating the same
10/31/2006US7130229 Interleaved mirrored memory systems
10/31/2006US7130228 Active termination control through module register
10/31/2006US7130227 Adjustable timing circuit of an integrated circuit
10/31/2006US7130226 Clock generating circuit with multiple modes of operation
10/31/2006US7130225 Charge pump with large bypass capacitors
10/31/2006US7130224 Composite storage circuit and semiconductor device having the same composite storage circuit
10/31/2006US7130211 Interleave control device using nonvolatile ferroelectric memory
10/31/2006US7129953 Two dimensional buffer pages
10/31/2006US7129869 Superconductor semiconductor integrated circuit
10/31/2006US7129549 Semiconductor integrated circuit device
10/31/2006US7129539 Semiconductor storage device and manufacturing method therefor, semiconductor device, portable electronic equipment and IC card
10/31/2006US7129503 Determining emitter beam size for data storage medium
10/31/2006CA2302013C Integrated dram with high speed interleaving
10/26/2006WO2006063312A3 Variable voltage supply bias and methods for negative differential resistance (ndr) based memory device
10/26/2006WO2006014395A3 Memory systems and methods
10/26/2006US20060242514 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same
10/26/2006US20060242495 Memory device having terminals for transferring multiple types of data
10/26/2006US20060242427 Credential interface
10/26/2006US20060242421 Logon system for an electronic device
10/26/2006US20060242367 Synchronizing memory copy operations with memory accesses
10/26/2006US20060239099 No-precharge FAMOS cell and latch circuit in a memory device
10/26/2006US20060239098 Dram architecture enabling refresh and access operations in the same bank
10/26/2006US20060239097 Semiconductor storage apparatus
10/26/2006US20060239096 Memory structure and memory refreshing method
10/26/2006US20060239095 Memory device communication using system memory bus
10/26/2006US20060239094 Semiconductor memory including self-timing circuit
10/26/2006US20060239093 Semiconductor memory device
10/26/2006US20060239092 Memory Circuit And Related Method For Integrating Pre-Decoding And Selective Pre-Charging
10/26/2006US20060239088 Method and apparatus for increasing fuse programming yield through preferred use of duplicate data
10/26/2006US20060239087 Method of generating an internal clock for a semiconductor memory device and semiconductor memory device using the same
10/26/2006US20060239086 Nonvolatile memory system
10/26/2006US20060239085 Dynamic shift register
10/26/2006US20060239084 Output buffer circuit for semiconductor memory device
10/26/2006US20060238908 Timing control circuit for an optical recording apparatus
10/26/2006US20060238216 Semiconductor integrated circuit
10/26/2006US20060237473 Delay locked loop fine tune
10/26/2006DE10339047B4 Treiber-Einrichtung, insbesondere für ein Halbleiter-Bauelement, sowie Verfahren zum Betreiben einer Treiber-Einrichtung Driver means, in particular for a semiconductor device, and method for operating a device driver
10/26/2006DE10332314B4 Halbleiterspeicher mit kurzer effektiver Wortleitungszykluszeit sowie Verfahren zum Lesen von Daten aus einem derartigen Halbleiterspeicher A semiconductor memory having a short effective word line cycle time and method for reading data from such a semiconductor memory
10/26/2006DE102005030874B3 Non-volatile memory e.g. ROM, cell state detecting method, involves keeping voltage of one capacitance constant, so that current of another capacitance flows to cell arrangement and through memory cell
10/26/2006DE102004050927B4 Nichtflüchtiges Halbleiterspeicherbauelement The non-volatile semiconductor memory device
10/25/2006EP1714288A2 Secured phase-change devices
10/25/2006EP1714287A1 Method and system for providing temperature dependent programming for magnetic memories
10/25/2006EP1388207A4 Apparatus/method for distributing a clock signal
10/25/2006CN1853238A Method and apparatus for implicit DRAM precharge
10/25/2006CN1853174A Method and device for operating electronic semiconductor components via signal lines
10/25/2006CN1851823A Magnetic random access memory device
10/25/2006CN1851821A Semiconductor memory and method for adjustment phase relation between clock signal and strobe signal
10/25/2006CN1851817A Automatic regulating method of Mips number operated during decoder decoding process
10/25/2006CN1851778A Intelligent child-rearing auxiliary system based on multimedia technology
10/25/2006CN1282197C Magnetic random-access storage device and reading method thereof
10/24/2006US7127566 Synchronizing memory copy operations with memory accesses
10/24/2006US7127552 Using transfer bits during data transfer from non-volatile to volatile memories
10/24/2006US7127306 Recording and/or reproducing apparatus and recording apparatus
10/24/2006US7126873 Method and system for expanding flash storage device capacity
10/24/2006US7126871 Circuits and methods to protect a gate dielectric antifuse
10/24/2006US7126870 Integrated semiconductor memory with sense amplifier
10/24/2006US7126869 Sense amplifier with dual cascode transistors and improved noise margin
10/24/2006US7126868 Semiconductor device
10/24/2006US7126867 Semiconductor memory device for low power system
10/24/2006US7126866 Low power ROM architecture
10/24/2006US7126865 Memory device including parallel test circuit
10/24/2006US7126864 Memory device capable of changing data output mode
10/24/2006US7126863 Active termination control
10/24/2006US7126861 Programmable control of leakage current
10/24/2006US7126860 Read-accessible column latch for non-volatile memories
10/24/2006US7126858 Apparatus for emulating asynchronous clear in memory structure and method for implementing the same
10/24/2006US7126857 Storage subsystem with embedded circuit for protecting against anomalies in power signal from host
10/24/2006US7126853 Electronic memory having impedance-matched sensing
10/24/2006US7126851 Method of transferring initially-setting data in a non-volatile semiconductor memory
10/24/2006US7126850 Semiconductor nonvolatile memory device
10/24/2006US7126845 Memory device capable of performing high speed reading while realizing redundancy replacement
10/24/2006US7126838 Readout circuit, solid state image pickup device using the same circuit, and camera system using the same
10/24/2006US7126434 Oscillator circuit for semiconductor device
10/24/2006US7126408 Method and apparatus for receiving high-speed signals with low latency
10/24/2006US7126379 Output device for static random access memory
10/24/2006US7126196 Self-testing printed circuit board comprising electrically programmable three-dimensional memory
10/24/2006US7126151 Interconnected high speed electron tunneling devices
10/19/2006WO2006110239A1 Y-mux splitting scheme
10/19/2006WO2006109849A1 Catalyst for catalytically reducing nitrogen oxide, catalyst structure, and method of catalytically reducing nitrogen oxide
10/19/2006WO2006065698A3 Sense amplifier circuitry and architecture to write data into and/or read data from memory cells
10/19/2006WO2006058892A3 Memory system with sector buffers
10/19/2006WO2005119234B1 Measuring device and methods for use therewith