| Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197) |
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| 05/09/2006 | US7043515 Methods and apparatus for modular reduction circuits |
| 05/09/2006 | US7043382 Low voltage swing bus analysis method using static timing analysis tool |
| 05/09/2006 | US7042800 Method and memory system in which operating mode is set using address signal |
| 05/09/2006 | US7042799 Write circuit of double data rate synchronous DRAM |
| 05/09/2006 | US7042796 Bank command decoder in semiconductor memory device |
| 05/09/2006 | US7042795 Flash memory device with burst read mode of operation |
| 05/09/2006 | US7042791 Multi-port memory device with global data bus connection circuit |
| 05/09/2006 | US7042789 Energy storing memory circuit |
| 05/09/2006 | US7042788 Power supply circuit and semiconductor storage device with the power supply circuit |
| 05/09/2006 | US7042787 Semiconductor integrated circuit device |
| 05/09/2006 | US7042786 Memory with adjustable access time |
| 05/09/2006 | US7042785 Method and apparatus for controlling refresh cycles of a plural cycle refresh scheme in a dynamic memory |
| 05/09/2006 | US7042784 Nonvolatile ferroelectric memory device with split word lines |
| 05/09/2006 | US7042783 Magnetic memory |
| 05/09/2006 | US7042782 Bit line sense amplifier for inhibiting increase of offset voltage |
| 05/09/2006 | US7042781 Semiconductor memory device for reducing write recovery time |
| 05/09/2006 | US7042780 Semiconductor integrated circuit and method for detecting soft defects in static memory cell |
| 05/09/2006 | US7042779 Method and apparatus for reducing leakage current in a read only memory device using pre-charged sub-arrays |
| 05/09/2006 | US7042778 Flash array implementation with local and global bit lines |
| 05/09/2006 | US7042777 Memory device with non-variable write latency |
| 05/09/2006 | US7042776 Method and circuit for dynamic read margin control of a memory array |
| 05/09/2006 | US7042775 Semiconductor memory with wordline timing |
| 05/09/2006 | US7042774 Semiconductor memory device to supply stable high voltage during auto-refresh operation and method therefor |
| 05/09/2006 | US7042773 Integrated circuit for storing operating parameters |
| 05/09/2006 | US7042771 Method and apparatus for synchronization of row and column access operations |
| 05/09/2006 | US7042770 Memory devices with page buffer having dual registers and method of using the same |
| 05/09/2006 | US7042769 Semiconductor memory device capable of accurate and stable operation |
| 05/09/2006 | US7042768 Flash memory architecture for optimizing performance of memory having multi-level memory cells |
| 05/09/2006 | US7042760 Phase-change memory and method having restore function |
| 05/09/2006 | US7042759 Dynamic data restore in thyristor-based memory device |
| 05/09/2006 | US7042758 Magnetic cell and magnetic memory |
| 05/09/2006 | US7042757 1R1D MRAM block architecture |
| 05/09/2006 | US7042756 Configurable storage device |
| 05/09/2006 | US7042755 High density non-volatile memory device |
| 05/09/2006 | US7042750 Read only memory devices with independently precharged virtual ground and bit lines |
| 05/09/2006 | US7042749 Stacked 1T-nmemory cell structure |
| 05/09/2006 | US7042301 Crystal oscillator emulator |
| 05/09/2006 | US7042206 Integrated circuit and method for operating the integrated circuit |
| 05/09/2006 | CA2420378C Non-volatile passive matrix and method for readout of the same |
| 05/04/2006 | WO2006047089A2 Memory output data systems and methods with feedback |
| 05/04/2006 | WO2005091714A3 Apparatus and methods for multi-level sensing in a memory array |
| 05/04/2006 | US20060095808 Method and apparatus for using internal delays for adjusting setup and hold times in a memory device |
| 05/04/2006 | US20060095381 Reproducing apparatus and reproducing method |
| 05/04/2006 | US20060092744 Power supply control circuit and controlling method thereof |
| 05/04/2006 | US20060092743 Semiconductor memory device and internal voltage generating method thereof |
| 05/04/2006 | US20060092741 Self refresh circuit of PSRAM for real access time measurement and operating method for the same |
| 05/04/2006 | US20060092740 Multiport semiconductor memory device |
| 05/04/2006 | US20060092739 Semiconductor memory device |
| 05/04/2006 | US20060092738 Semiconductor memory device for low power system |
| 05/04/2006 | US20060092737 Memory and semiconductor device |
| 05/04/2006 | US20060092736 Integrated semiconductor memory device including sense amplifiers |
| 05/04/2006 | US20060092735 Method for measuring offset voltage of sense amplifier and semiconductor employing the method |
| 05/04/2006 | US20060092734 Read circuit of semiconductor memory |
| 05/04/2006 | US20060092733 Semiconductor memory device for low power system |
| 05/04/2006 | US20060092732 Semiconductor memory device for low power system |
| 05/04/2006 | US20060092731 Semiconductor memory device for low power system |
| 05/04/2006 | US20060092730 Semiconductor memory device for low power condition |
| 05/04/2006 | US20060092727 Flood mode implementation for continuous bitline local evaluation circuit |
| 05/04/2006 | US20060092723 Data input/output method of semiconductor memory device and semiconductor memory device for the same |
| 05/04/2006 | US20060092722 Data arrangement control signal generator for use in semiconductor memory device |
| 05/04/2006 | US20060092721 Memory system, a memory device, a memory controller and method thereof |
| 05/04/2006 | US20060092720 Semiconductor memory |
| 05/04/2006 | US20060092719 Semiconductor memory device |
| 05/04/2006 | US20060092718 Flash memory data bus for synchronous burst read page |
| 05/04/2006 | US20060092717 Methods and computer program products for determining simultaneous switching induced data output timing skew |
| 05/04/2006 | US20060092716 Memory devices using tri-state buffers to discharge data lines, and methods of operating same |
| 05/04/2006 | US20060092715 Circuit |
| 05/04/2006 | US20060092714 Semiconductor memory device with simplified data control signals |
| 05/04/2006 | US20060092713 Synchronous memory open page register |
| 05/04/2006 | US20060092712 Branch target buffer and method of use |
| 05/04/2006 | US20060092711 Efficient implementation of a read scheme for multi-threaded register file |
| 05/04/2006 | US20060092710 Efficient method of data transfer between register files and memories |
| 05/04/2006 | DE102005029874A1 On-die termination circuit of semiconductor memory device, generates pull-up and pull-down control signals for turning on and off multiple output driver units in response to output signals of decoding unit |
| 05/04/2006 | DE102004052612A1 Halbleiterspeicherbaustein, Halbleiterspeichermodul und Verfahren zur Übertragung von Schreibdaten zu Halbleiterspeicherbausteinen Semiconductor memory device, the semiconductor memory module and method for transmitting write data to semiconductor memory chips |
| 05/04/2006 | DE102004052268A1 Semiconductor memory system, uses zones with non-masked clock-signal flanks for identifying the clock signal |
| 05/04/2006 | DE102004051152A1 NOR- und NAND-Speicheranordnung von resistiven Speicherelementen NOR and NAND memory array of resistive memory elements |
| 05/03/2006 | EP1653340A1 Storage device and information processing system |
| 05/03/2006 | EP1652178A1 A recording medium, method of configuring control information thereof, method for recording or reproducing data using the same, and apparatus thereof |
| 05/03/2006 | EP1470553B1 Apparatus and method for encoding auto-precharge |
| 05/03/2006 | CN1768391A Column-decoding and precharging in a flash memory device |
| 05/03/2006 | CN1767068A Non-volatile memory device |
| 05/03/2006 | CN1767065A Data output driver for reducing noise |
| 05/03/2006 | CN1767064A Sense amplifier with low common mode differential input signal |
| 05/03/2006 | CN1767063A Semiconductor memory device for low power condition |
| 05/03/2006 | CN1767062A Semiconductor memory device for low power system |
| 05/03/2006 | CN1767061A Integral semiconductor storage with tempo generation |
| 05/03/2006 | CN1767060A Semiconductor memory device for low power system |
| 05/03/2006 | CN1767059A Method for measuring offset voltage of sense amplifier and semiconductor employing the method |
| 05/03/2006 | CN1767058A Semiconductor memory device with simplified data control signals |
| 05/03/2006 | CN1767057A Semiconductor memory device for low power condition |
| 05/03/2006 | CN1767056A Control unit for reading wait time |
| 05/03/2006 | CN1767055A Delay locked loop and locking method thereof |
| 05/03/2006 | CN1767054A Memory device |
| 05/03/2006 | CN1767052A Process for improving feedback clock interface of high-speed dynamic synchronous random storage |
| 05/03/2006 | CN1767051A Programmable storing apparatus and method |
| 05/03/2006 | CN1767050A Programmable storing apparatus and method |
| 05/03/2006 | CN1767049A Method for driving variable resistor element and storage device |
| 05/03/2006 | CN1767048A Latch clock generation circuit and serial-parallel conversion circuit |
| 05/03/2006 | CN1767047A Method for programming a multilevel phase change memory device |
| 05/03/2006 | CN1766912A Process for initializing memory card |