Patents
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
06/2006
06/08/2006US20060120168 Semiconductor device, nonvolatile semiconductor memory, system including a plurality of semiconductor devices or nonvolatile semiconductor memories, electric card including semiconductor device or nonvolatile semiconductor memory, and electric device with which this electric card can be used
06/08/2006US20060120167 Design analysis tool and method for deriving correspondence between storage elements of two memory models
06/08/2006US20060120164 Nonvolatile memory system, semiconductor memory, and writing method
06/08/2006US20060120163 Current mirror with programmable floating gate
06/08/2006US20060120131 System and method for communicating information to a memory device using a reconfigured device pin
06/08/2006US20060120129 Memory cell array
06/08/2006US20060119500 Digital-to-analog converter with programmable floating gate
06/08/2006US20060119499 Analog-to-digital converter with programmable floating gate
06/08/2006US20060119317 Battery pack with built in communication port
06/08/2006DE102005057112A1 Nichtflüchtiges Speicherbauelement und Programmierverfahren Non-volatile memory device and programming method
06/08/2006DE102005055853A1 Transistor-Feld für Halbleiterspeicherbauelemente und Verfahren zum Herstellen eines Feldes von Transistoren mit vertikalem Kanal Transistor field for semiconductor memory devices and methods of manufacturing an array of transistors with a vertical channel
06/08/2006DE102005055185A1 Halbleiterspeichermodul A semiconductor memory module
06/08/2006DE102004057231A1 Verfahren zum Übertragen eines elektrischen Signals und Ausgangstreiberschaltung für ein zu übertragendes elektrisches Signal A method of transmitting an electrical signal and output driver circuit for an electrical signal to be transmitted
06/08/2006DE102004056911A1 Speicherschaltung sowie Verfahren zum Auslesen eines Speicherdatums aus einer solchen Speicherschaltung Memory circuit and method for reading out a datum from memory of such a memory circuit
06/08/2006DE10124753B4 Schaltungsanordnung zum Auslesen und zum Speichern von binären Speicherzellensignalen Circuit arrangement for reading and storing binary memory cell signals
06/08/2006CA2589360A1 Memory system with sector buffers
06/07/2006EP1667162A1 Control circuit and semiconductor memory device
06/07/2006EP1667161A1 Dual loop sensing scheme for resistive memory elements
06/07/2006EP1665275A2 Method and apparatus for read bitline clamping for gain cell dram devices
06/07/2006EP1665273A2 Method and apparatus for reading and writing to solid-state memory
06/07/2006EP1537741A4 Remote user interface for media player
06/07/2006CN1783345A Non-volatile memory storage of fuse information
06/07/2006CN1783341A Multiport semiconductor memory device
06/07/2006CN1783340A Semiconductor memory chip, semiconductor memory module and method for transmitting write data to semiconductor memory chips
06/07/2006CN1783339A Circuit arrangement and method for setting operating parameters in a ram module
06/07/2006CN1783332A Reading and writing method of double speed dynamic random access memory
06/07/2006CN1783331A Semiconductor memory system and method for data transmission between memory controller and semiconductor memory
06/07/2006CN1783330A Memory device
06/07/2006CN1783329A Structure of sequencers that perform initial and periodic calibrations and method
06/07/2006CN1783328A Memory array with fast bit line precharge
06/07/2006CN1783028A Memory system,memory device and output data strobe signal generating method
06/07/2006CN1258769C Semiconductor storage device reading data according to current passing through storage unit while accessing
06/06/2006US7058776 Asynchronous memory using source synchronous transfer and system employing the same
06/06/2006US7058770 Method and apparatus for controlling the recording of digital information, by using unit management table
06/06/2006US7058756 Circuit for implementing special mode in packet-based semiconductor memory device
06/06/2006US7058653 Tree system diagram output method, computer program and recording medium
06/06/2006US7058285 Recording medium editing apparatus based on content supply source
06/06/2006US7057981 Disk array system and method for controlling disk array system
06/06/2006US7057970 Nonvolatile ferroelectric memory and control device using the same
06/06/2006US7057969 Self-timed sneak current cancellation
06/06/2006US7057968 Semiconductor integrated circuit device
06/06/2006US7057967 Multi-mode synchronous memory device and methods of operating and testing same
06/06/2006US7057966 Semiconductor memory device for reducing current consumption in operation
06/06/2006US7057965 Method of performing access to a single-port memory device, memory access device, integrated circuit device and method of use of an integrated circuit device
06/06/2006US7057964 Semiconductor memory device with efficient multiplexing of I/O pad in multi-chip package
06/06/2006US7057961 Circuit and method for evaluating and controlling a refresh rate of memory cells of a dynamic memory
06/06/2006US7057960 Method and architecture for reducing the power consumption for memory devices in refresh operations
06/06/2006US7057959 Semiconductor memory having mode register access in burst mode
06/06/2006US7057958 Method and system for temperature compensation for memory cells with temperature-dependent behavior
06/06/2006US7057957 High speed and low power sense amplifier
06/06/2006US7057956 Semiconductor integrated circuit device and method for testing the same
06/06/2006US7057955 Dynamically unbalanced sense amplifier
06/06/2006US7057954 Sense amplifier select circuit and method of selecting the same
06/06/2006US7057953 Semiconductor memory device with stable auto-precharge operation
06/06/2006US7057952 Precharge control circuit of pseudo SRAM
06/06/2006US7057951 Semiconductor memory device for controlling write recovery time
06/06/2006US7057950 Semiconductor memory devices with delayed auto-precharge function and associated methods of auto-precharging semiconductor memory devices
06/06/2006US7057949 Method and apparatus for pre-charging negative pump MOS regulation capacitors
06/06/2006US7057948 Semiconductor integrated circuit device having a test function
06/06/2006US7057947 Semiconductor device, nonvolatile semiconductor memory, system including a plurality of semiconductor devices or nonvolatile semiconductor memories, electric card including semiconductor device or nonvolatile semiconductor memory, and electric device with which this electric card can be used
06/06/2006US7057946 Semiconductor integrated circuit having latching means capable of scanning
06/06/2006US7057945 Non-volatile memory erase circuitry
06/06/2006US7057944 Semiconductor readout circuit
06/06/2006US7057943 Data output controller for memory device
06/06/2006US7057937 Data processing apparatus having a flash memory built-in which is rewritable by use of external device
06/06/2006US7057916 Small size ROM
06/06/2006US7057915 Pattern layout of word line transfer transistors in NAND flash memory which executes subblock erase
06/06/2006US7057914 Cross point memory array with fast access time
06/06/2006US7057441 Block selection circuit
06/06/2006US7057431 Digital DLL apparatus for correcting duty cycle and method thereof
06/06/2006US7057420 Semiconductor device having sense amplifier driver with capacitor affected by off current
06/06/2006US7057416 Enhanced protection for input buffers of low-voltage flash memories
06/06/2006US7057353 Electronic device with wide lens for small emission spot size
06/06/2006US7057201 Integrated semiconductor memory
06/06/2006US7056785 Non-volatile memory cell fabricated with slight modification to a conventional logic process and methods of operating same
06/01/2006WO2006058200A2 Micro-threaded memory
06/01/2006US20060117204 Apparatus and method for generating a delayed clock signal
06/01/2006US20060117150 Memory system comprising a plurality of memory controllers and method for synchronizing the same
06/01/2006US20060116780 Digital audio recording and reproducing apparatus
06/01/2006US20060114739 Method and circuit for controlling generation of a boosted voltage in devices receiving dual supply voltages
06/01/2006US20060114738 Non-volatile semiconductor memory device
06/01/2006US20060114736 Nonvolatile semiconductor memory cell and method of manufacturing the same
06/01/2006US20060114735 Semiconductor memory device and refresh control method
06/01/2006US20060114734 Temperature based DRAM refresh
06/01/2006US20060114733 Non-volatile semiconductor memory device
06/01/2006US20060114731 Method and apparatus for controlling a high voltage generator in a wafer burn-in test
06/01/2006US20060114730 Nonvolatile memory devices and programming methods using subsets of columns
06/01/2006US20060114729 Non-volatile semiconductor memory device and memory system using the same
06/01/2006US20060114728 Data storage device having multiple buffers
06/01/2006US20060114727 Audio visual architecture
06/01/2006US20060114726 Nonvolatile memory
06/01/2006US20060114706 Content addressable memory with reduced search current and power
06/01/2006US20060113535 Probe look ahead: testing parts not currently under a probehead
06/01/2006DE102005050595A1 Speichersystem, Speichervorrichtung, Speichersteuervorrichtung und Verfahren dafür Memory system, memory device, memory control device and method therefor
06/01/2006DE102004058220A1 Memory/storage module e.g. DRAM-storage device, uses control terminal for output driver circuit for influencing rise and fall rates of output signal
06/01/2006DE102004057763A1 Memory card for wireless data transmission has a PCB with a microprocessor and a conducting wire connected to an aerial which is glued to the PCB surface in an electrically conducting manner
06/01/2006DE102004057232A1 Semiconductor memory device operating method, involves setting preamble, which is number of clock cycles between edge of data clock signal and bit of data signals that are transmitted to and/or from semiconductor memory device
06/01/2006DE102004039422B4 Data memory arrangement, has access unit coupled with data output of addressing unit and designed for cyclic access on registers, where unit is designed for selection of memories and transmission of contents of data word
05/2006
05/31/2006EP1661138A1 Method and arrangement for the production of a memory chip having different data bit widths
05/31/2006EP1661137A2 Low voltage operation dram control circuits