Patents
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
06/2006
06/27/2006US7068563 Compact decode and multiplexing circuitry for a multi-port memory having a common memory interface
06/27/2006US7068561 Semiconductor memory device for controlling cell block with state machine
06/27/2006US7068560 High speed low voltage driver
06/27/2006US7068559 Word line enable timing determination circuit of a memory device and methods of determining word line enable timing in the memory device
06/27/2006US7068558 Semiconductor memory device having row path control circuit and operating method thereof
06/27/2006US7068556 Sense amplifier systems and methods
06/27/2006US7068555 Semiconductor memory storage device and a redundancy control method therefor
06/27/2006US7068554 Apparatus and method for implementing multiple memory redundancy with delay tracking clock
06/27/2006US7068553 Row redundancy circuit
06/27/2006US7068552 Sense amplifier
06/27/2006US7068551 Semiconductor memory device
06/27/2006US7068550 4-bit prefetch-type FCRAM having improved data write control circuit in memory cell array and method of masking data using the 4-bit prefetch-type FCRAM
06/27/2006US7068549 Circuit for generating data strobe signal in semiconductor device and method thereof
06/27/2006US7068548 Semiconductor integrated circuit with noise reduction circuit
06/27/2006US7068547 Internal voltage generating circuit in semiconductor memory device
06/27/2006US7068546 Integrated memory having a voltage generator circuit for generating a voltage supply for a read/write amplifier
06/27/2006US7068545 Data processing apparatus having memory protection unit
06/27/2006US7068536 Magnetic random access memory, and production method therefor
06/27/2006US7068535 Magnetic spin based memory with semiconductor selector
06/27/2006US7068534 Phase-change memory device with overvoltage protection and method for protecting a phase-change memory device against overvoltages
06/27/2006US7068528 Layout structure of bit line sense amplifier of semiconductor memory device
06/27/2006US7068281 Pixel pages optimized for GLV
06/27/2006US7068280 Method and apparatus to provide overlay buffering
06/27/2006US7068083 Synchronous output buffer, synchronous memory device and method of testing access time
06/27/2006US7068079 Circuit device with clock pulse detection facility
06/27/2006US7068078 Data output driver
06/27/2006US7068069 Control circuit and reconfigurable logic block
06/22/2006WO2006066167A1 Low-power receiver equalization in a clocked sense amplifier
06/22/2006WO2006065518A1 Pipelined programming of non-volatile memories using early data
06/22/2006WO2006065501A1 Memory sensing circuit and method for low voltage operation
06/22/2006WO2006064497A2 A method of handling limitations on the order of writing to a non-volatile memory
06/22/2006WO2006033581A9 Read method and sensing device
06/22/2006WO2005050382A3 System and method for data storage and tracking
06/22/2006US20060136692 Detection circuit for mixed asynchronous and synchronous memory operation
06/22/2006US20060133189 N-well and N+ buried layer isolation by auto doping to reduce chip size
06/22/2006US20060133182 Semiconductor memory device for reducing peak current during refresh operation
06/22/2006US20060133180 Semiconductor memory device and semiconductor integrated circuit device
06/22/2006US20060133174 Phase-change RAM containing AIN thermal dissipation layer and TiN electrode
06/22/2006US20060133173 Method, apparatus, and system for active refresh management
06/22/2006US20060133172 Apparatus and method for writing to and/or reading from a memory cell in a semiconductor memory
06/22/2006US20060133171 Readout circuit and nonvolatile semiconductor memory device
06/22/2006US20060133170 Memory circuit
06/22/2006US20060133169 Address comparator of semiconductor memory device
06/22/2006US20060133168 Semiconductor memory device for reducing chip area
06/22/2006US20060133167 Nonvolatile semiconductor memory device using irreversible storage elements
06/22/2006US20060133165 Memory system and method for strobing data, command and address signals
06/22/2006US20060133164 Semiconductor memory with wordline timing
06/22/2006US20060133163 Circuit arrangement and method for switching high-voltage signals by means of low-voltage signals
06/22/2006US20060133162 Self-latched control circuit for memory program operation
06/22/2006US20060133160 Bufferless writing of data to memory
06/22/2006US20060133159 Method for transmission and reception of a data signal on a line pair, as well as a transmission and reception circuit for this purpose
06/22/2006US20060133158 Pipe latch circuit of multi-bit prefetch-type semiconductor memory device with improved structure
06/22/2006US20060133157 Method of handling limitations on the order of writing to a non-volatile memory
06/22/2006US20060133139 Non-volatile semiconductor memory
06/22/2006US20060133128 Method and storage device for the permanent storage of data
06/22/2006DE102004054819B3 Elektronische Schaltungsanordnung mit aktiver Regelung bei einem Empfang eines elektrischen Empfangssignals An electronic circuit with active control in a receipt of an electrical signal reception
06/21/2006EP1671357A2 Circuit and method for controlling a clock synchronizing circuit for low power refresh operation
06/21/2006EP1671352A2 Integrated circuit power management for reducing leakage current in circuit arrays and method therefor
06/21/2006CN2789888Y MP3 and matched receiver-player
06/21/2006CN2789887Y Wireless vehicular MP3-U music player
06/21/2006CN1791941A Read and erase verify methods and circuits suitable for low voltage non-volatile memories
06/21/2006CN1790547A Sram with dynamically asymmetric cell
06/21/2006CN1790545A Memory selecting signal control circuit and method used in semiconductor storge device
06/21/2006CN1790544A 半导体存储器装置 The semiconductor memory device
06/21/2006CN1790543A Method for generating magnetic RAM reference signal
06/21/2006CN1790540A Memory and semiconductor device
06/21/2006CN1790291A Method and device for managing array redundancy data
06/21/2006CN1790290A System and method for preventing unauthorized access to proprietatary information in IC device
06/21/2006CN1260737C Memory module
06/21/2006CN1260735C Memory with processing function
06/21/2006CN1260733C Semiconductor memory and method for accessing semiconductor memory
06/21/2006CN1260068C Cartridge and recording apparatus
06/20/2006US7065689 Diagonal testing method for flash memories
06/20/2006US7065687 Method for replacing defective memory cells in data processing apparatus
06/20/2006US7065666 Apparatus and method for generating a delayed clock signal
06/20/2006US7065417 MPEG portable sound reproducing system and a reproducing method thereof
06/20/2006US7065135 System and method for equalizing high-speed data transmission
06/20/2006US7065003 Latency control circuit and method of latency control
06/20/2006US7064999 Digital memory circuit having a plurality of memory banks
06/20/2006US7064998 Semiconductor memory
06/20/2006US7064997 Memory circuit with automatic precharge function, and integrated circuit device with automatic internal command function
06/20/2006US7064996 Refreshing dynamic memory cells in a memory circuit and a memory circuit
06/20/2006US7064994 Dynamic memory throttling for power and thermal limitations
06/20/2006US7064993 Semiconductor memory device with common I/O type circuit configuration achieving write before sense operation
06/20/2006US7064992 Method and apparatus for saving current in a memory device
06/20/2006US7064991 Semiconductor storage device
06/20/2006US7064990 Method and apparatus for implementing multiple column redundancy for memory
06/20/2006US7064989 On-die termination control circuit and method of generating on-die termination control signal
06/20/2006US7064988 Synchronous semiconductor memory device of fast random cycle system and test method thereof
06/20/2006US7064987 Memory address generator with scheduled write and read address generating capability
06/20/2006US7064983 Method for programming a reference cell
06/20/2006US7064977 Reference cells for TCCT based memory cells
06/20/2006US7064976 Method of operating a stacked spin based memory
06/20/2006US7064571 Multiple-select multiplexer circuit, semiconductor memory device including a multiplexer circuit and method of testing the semiconductor memory device
06/20/2006US7064376 High performance embedded semiconductor memory devices with multiple dimension first-level bit-lines
06/20/2006US7064018 Methods for fabricating three dimensional integrated circuits
06/15/2006WO2006063001A2 Power line communication system with automated meter reading
06/15/2006WO2006062922A2 Power line repeater system and method
06/15/2006WO2006061118A1 Buffer chip for a multi-rank dual inline memory module (dimm)
06/15/2006WO2006017686A3 Enhanced techniques for using core based nodes for state transfer